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We report the fabrication and characteristic analysis of ZnO thin film transistors (TFTs) having two different active layer thicknesses such as 40nm and 80nm, using RF magnetron sputter. At first, there is a positive voltage shift in all devices under the gate-bias stress, which is more manifest in TFTs with active layer thickness of 40 nm than 80nm. However, when the stress bias is removed, all ZnO TFTs recover their original characteristics, which are regarded as a result of rather preexisting traps than created traps. In addition, it is known that the thinner active layer thickness is, the smaller grain size is through XRD analysis. In order to clarify the comparison of preexisting traps according to the active layer thickness, the grain boundary traps by Levinson's model and Hooge's parameters by Hooge's model are extracted. From above results, TFTs with active layer thickness of 40 nm exposes higher grain boundary trap density and Hooge's parameter value. Consequently, we can see that the number of preexisting traps in the device increases in accordance with the decrease in the grain size. [ABSTRACT FROM AUTHOR]

In this paper, the electrical characteristics of Fin-type flash memory device are analyzed in depth with different trapping layer. Compared to the Planar-type device, Fin-type flash memory device shows good short-channel effect immunity and high punch-through margin. We fabricated the Fin-type SOHOS (Silicon-Oxide-High-K-Oxide-Silicon) flash memory device with hafnium oxide (HfO2) trapping layer and compared with the Fin-type SONOS flash memory device. The fabricated Fin-type SOHOS device shows superior program/erase speed and exhibits poorer retention characteristic. The inferior data retention in the SOHOS device may be attributed to tunneling leakage current induced by interface trap states. This expectation is supported by the charge pumping technique and low frequency noise characteristics. [ABSTRACT FROM AUTHOR]