Search

This paper presents the development and thorough analysis of a wide range of coplanar-waveguide circular spiral inductors with remarkably high performance and inductance density using advanced multilayer (ML) photoimageable thick-film (Pimage-TF) multichip module (MCM) technology. The performances of the embedded spiral inductors are thoroughly analyzed, modeled, and compared with the competitive MCM technologies and are superior to most of the published results. A new design and layout generation technique with a simplified closed form expression for circular spiral inductors is proposed. Moreover, the impact of MCM/system-on-package technologies on inductor key parameters has been explained in detail and compared with other technologies. The cost-effective Pimage-TF-based inductors demonstrate the highest level of self-resonance frequency, as well as inductance density (15 nH/ \mathrmmm^\mathrm \mathbf 2 ) reported to date in conventional thick-film-based ML MCM technologies, including low temperature cofired ceramic. [ABSTRACT FROM PUBLISHER]

This paper presents an approach for the extraction of passive macromodels of large-scale interconnects from their frequency-domain scattering responses. Here, large scale is intended both in terms of number of electrical ports and required dynamic model order. For such structures, standard approaches based on rational approximation via vector fitting and passivity enforcement via model perturbation may fail because of excessive computational requirements, both in terms of memory size and runtime. Our approach addresses this complexity by first reducing the redundancy in the raw scattering responses through a projection and approximation process based on a truncated singular value decomposition. Then we formulate a compressed rational fitting and passivity enforcement framework which is able to obtain speedup factors up to 2 and 3 orders of magnitude with respect to standard approaches, with full control over the approximation errors. Numerical results on a large set of benchmark cases demonstrate the effectiveness of the proposed technique. [ABSTRACT FROM AUTHOR]

Interconnects in radio frequency (RF) packages have a strong tendency to deteriorate RF performance, especially in high-frequency systems. In this paper, comparison is made between the wirebonded and embedded flip-chip packages. X-band silicon-germanium low-noise amplifiers are used to evaluate the performance of these interconnects. Measured results show that the embedded flip-chip packages have better RF performance than the wirebonded packages for X-band applications. At 9.5 GHz, the flip-chip interconnects contribute only 0.4 dB of insertion loss, while the wirebond interconnects contribute 2.2 dB of insertion loss. The flip-chip and wirebond interconnects are modeled and validated against measured results from 8 to 20 GHz. For the first time, multiple dies are put together in a single liquid crystal polymer package to compare the packaging effects, and to demonstrate the feasibility of embedding multiple dies within a single package for highly integrated solutions. [ABSTRACT FROM PUBLISHER]

In this investigation, Cu-Sn lead-free solder microbumps on 10-μm pads with a 20-μm pitch are designed and fabricated. The chip size is 5 × 5 mm with thousands of microbumps. A daisy-chain feature is adopted for the characterization and reliability assessment. After pattern trace formation, the microbump is fabricated on the trace by an electroplating technique. A suitable barrier/seed layer thickness is designed and applied to minimize the undercut due to wet etching but to still achieve good plating uniformity. With the current process, the undercut is less than 1 μm and the bump height variation is less than 10%. In addition, the shear test is adopted to characterize the bump strength, which exceeds the specification. Also, the Cu-Sn lead-free solder microbumped chip is bonded on an Si wafer using chip-to-wafer bonding technique. Furthermore, the microgap between the bonded chips is filled with a special underfill. The shear strength of the bonded chips without the underfill is measured and it exceeds the specification. The bonding and filling integrity is further evaluated by open/short measurement, scanning acoustic tomography analysis, and cross-section with scanning electron microscopy analysis. The stacked ICs are evaluated by reliability (thermal cycling) test (-55 to 125°C). Finally, ultrafine-pitch (5-μm pads on a 10-μm pitch) lead-free solder microbumping is explored. [ABSTRACT FROM PUBLISHER]

Application of electronic devices on automotive vehicles keeps increasing, and adoption of ball grid array (BGA) package is inevitable in the industry. Vibration loading to a vehicle provides another hazardous stress to the BGA assembly in addition to thermal one. In this paper, random vibration test on a daisy-chained BGA assembly is conducted with a real-time monitoring of resistance. BGA assemblies with leaded and lead-free solders are tested at once in the test. The changes of resistance before the occurrence of failure are investigated and a precursory resistance pattern before the failure of BGA assemblies is identified at the both solder types. Analyses on the failure locations confirm the localized failures on the BGA ball matrix. To investigate the generating mechanism of the precursory resistance pattern in the BGA assemblies, a numerical model of the mechanism is suggested and experimentally demonstrated. Based on the studies, a noble design of BGA assembly is suggested for the implementation of prognostics and health monitoring in vibration environment. [ABSTRACT FROM PUBLISHER]

The epoxy mold compound (EMC) used in encapsulated microelectronic devices affects the thermal, electrical and mechanical performance of the devices. Although many studies have been conducted to test the reliability, thermal and mechanical aspects of the problem not much literature can be found analyzing the impact of the mold compound on the electrical performance of the devices. In this paper we present the results of carefully designed experiments that evaluate the effects of the EMC in the electrical performance of high-power high-frequency laterally diffused metal oxide silicon transistors. [ABSTRACT FROM PUBLISHER]

A direct and deleterious effect on packaging reliability has been observed during elevated temperature isothermal aging for fine-pitch ball grid array (BGA) packages with Sn-1.0Ag-0.5Cu (SAC105), Sn-3.0Ag-0.5Cu (SAC305), and Sn-37Pb solder ball interconnects. Package sizes ranging from 19 mm with 0.8-mm-pitch BGAs to 5 mm with 0.4-mm-pitch μ BGAs with three different board finishes (ImSn, ImAg, and SnPb) were evaluated. The aging temperatures were 25°C, 55°C, 85°C, and 125°C, applied for a period of 6 mo. Subsequently, the specimens were thermally cycled from -40°C to 125°C with 15-min dwell times at the high temperature. Weibull analysis of failures versus cycle number show a ~ 50% reduction in package lifetimes when aged at 125°C compared to the same at room temperature, with less dramatic but measurable reductions in lifetime at 85°C and even 55°C. In contrast, the reliability performance of Sn-37Pb is much more stable over time and temperature. The degradation was observed for both SAC alloys on all tested package sizes and board finishes. For the 19-mm SAC105 case, for example, there was a 53% (32%) reduction of characteristic lifetime at 125°C (85°C) compared to room temperature aging. The trends were in the expected directions; namely, the reliability was reduced when using higher aging temperatures, smaller solder balls, and SAC105. The dominant failure mode can be associated with the growth of Cu6Sn5 intermetallic compounds during the aging, particularly on the pad side. [ABSTRACT FROM AUTHOR]

In recent years, there has been growing demand to increase the power density in power modules. Therefore, the thermal management of power modules has become more and more critical. In this paper, we show that conventional single-sided power module with wire-bond connection cannot achieve both good steady-state and transient thermal performance under high heat transfer coefficient conditions. The plate-bonded power module has been proposed to resolve this issue. However, the thick copper plate embedded in the power module induces large thermomechanical stress during temperature cycling, leading to poor reliability. To reduce the thermomechanical stress without significantly compromising the thermal performance, a trenched copper plate power module is designed and presented. A parametric study shows that the maximum von Mises stress and plastic strain in the solder layer can be reduced by 18.7%, and 67.8%, respectively, if the single piece of copper plate is replaced by a 3 × 3 trenched copper plate. [ABSTRACT FROM PUBLISHER]

In thermosonic wire bonding, a free air ball (FAB) created by electronic flame-off (EFO) is crucial to a reliable first bond. To reveal the mechanisms of FAB and ripple formation, the dynamic FAB formation process was monitored and analyzed with a high-speed camera and digital data acquisition system. FAB formation was found to occur in four stages: initiation, preheating, melting, and solidification. The FAB formation speed and model depend only on the EFO current. The FAB formation speed can be as high as 90.4 μm/ms at an EFO current of 60 mA. A minimum EFO time is required for FAB formation, which depends on the EFO current. A semiempirical model FAB=ηln[I(t - 0.5 tmin)]- c, was developed to describe the relationship between the FAB size and the EFO time at different EFO currents. The ripple formation mechanism was investigated by analyzing the solidification stage images. Transient droplet vibration caused by high-speed rolling-up and skin-forming solidification in the molten gold drop caused by a large temperature gradient are two major factors in ripple formation. This analysis is expected to be useful for understanding the FAB formation mechanism and optimizing the EFO parameters. [ABSTRACT FROM PUBLISHER]

The framework for this paper is the growing concern about the worldwide increasing energy consumption of telecommunications systems and data centers, and particularly the contribution of the thermal management system. The present energy usage of these systems is discussed, as well as the relationship between cooling system design and the total cost of ownership. This paper identifies immediate and future thermal bottlenecks facing the industry, ranging from technological issues at the component and system level to more general needs involving reliability, modularity, and multidisciplinary design. Based on this enumeration, the main challenges to implementing cooling solutions are reviewed. Particular attention is paid to implementing liquid cooling, since this technology seems the most promising to addressing the key thermal bottlenecks, and improving the future sustainability of thermal management in the telecom and data center industry. Finally, an outlook is presented toward future potential challenges. [ABSTRACT FROM PUBLISHER]

This paper deals with 24-GHz circuits developed by exploiting a system-in-package approach. In order to reduce the cost as much as possible, a standard multilayer printed circuit board (PCB) technology has been adopted. Such a circuit consists of a package built utilizing a 0.3-mm thick fiber-glass substrate with 3.38 relative permittivity. The contacts between the substrate and the mother board are realized along the package perimeter exploiting 0.6-mm via-hole metalization and half halo shield soldering pad. First, the developed package is simulated and optimized by means of commercial electromagnetic software. Then a prototype is fabricated and measured. The obtained results show that the whole frequency band from DC to 30 GHz can be covered. A packaged 26.5-mm straight microstrip line exhibits an |S11| value better than -12 dB and an |S21| value of about -1.4 dB at 24 GHz. This value is only 0.6-dB worse than that of the unpackaged line. A single-balanced diode mixer and a low-noise amplifier (LNA) for industrial, scientific, and medical applications are then designed. The integration of these building blocks within the PCB package is finally demonstrated and experimentally verified. The packaged mixer shows a 6.8-dB conversion loss. The packaged LNA, instead, features a 9.1-dB gain with a 3.4-dB noise figure. [ABSTRACT FROM PUBLISHER]

We investigate high-quality (high-Q) inductors implemented in the redistribution layer (RDL) of the fan-in and fan-out area of an embedded wafer-level ball grid array (eWLB) package. The eWLB is an innovative package technology introduced recently for wireless applications. The technology has outstanding capabilities especially for high-frequency and millimeter-wave package design. We demonstrate that inductors realized in the eWLB fan-out area have negligible substrate losses and lower parasitic capacitances compared to inductors in the eWLB fan-in area. As a result, the inductors implemented in the fan-out area offer significantly higher quality factors and higher self-resonance frequencies. We investigate the effects of the chip-to-package interconnection. We show that the chip-to-package transition creates a bottleneck for the integration of high-Q inductors. We demonstrate the advantages of inductors in the fan-out area of the eWLB on the example of a 6-GHz voltage-controlled oscillator (VCO) chip manufactured in a 65-nm complementary metal-oxide-semiconductor process and assembled in an eWLB package. For the LC tank of this example, we use a 1.1-nH high-Q differential fan-out eWLB inductor to reduce the phase noise. For comparison, we investigate a VCO fabricated with a standard on-chip inductor and assembled in the identical eWLB package. Our measurement results demonstrate lower phase noise and higher output power for all VCOs with inductors embedded in the RDL compared to the reference VCO with the on-chip inductor. The measured phase noise for the VCO with the eWLB inductor in the fan-out area is in the best case 9 dB lower than that of the reference VCO with the on-chip inductor. The presented results prove the integration concept and demonstrate the excellent potential of embedded inductors realized in the fan-out area of the eWLB package. [ABSTRACT FROM PUBLISHER]

This paper focused on the feasibility of preparing Sn-Ag-In ternary solder bumps with small size by two-step electroplating. The interfacial reaction and shear strength between three different solders (Sn2.2Ag, Sn1.8Ag9.4In, and Sn1.6Ag21.7In) and Cu under bump metallization (UBM) were investigated. After the reflow for 10 min, η Cu6(Sn,In)5 and ε Cu3(Sn,In) intermetallic compounds (IMC) were formed at the interface near the solder matrix and Cu UBM, respectively. Indium addition lowered the reflow temperature and improved the interface between solder and IMCs. The mean shear strength of Sn1.8Ag9.4In solder bump was higher than that of Sn2.2Ag and Sn1.6Ag21.7In solder bumps. After long time reflow, the mean shear strength increased. [ABSTRACT FROM PUBLISHER]

A detailed analysis of using three-dimensional electronics (3DE) to build a high-performance computational system has been completed. The overall goals were to maximize system performance, minimize system redesign, and optimize 3DE costs. Reliable and high-quality power distribution was identified as the most critical technical issue, with thermal effects being important as well. The use of 3-D vias on a standard grid is shown to be a valuable design option. A 3DE-based system using a three-tier 3DIC design (called a 3DC64) was defined and evaluated. Raw performance for the 3DC64 is expected to be up to 2× that of the current system (2DC64). The 3DC64 also demonstrated clear improvements in more critical metrics such as Operations/Watt and Operations/Dollar. Based on this analysis, some suggestions for research initiatives and optimum use of 3DE are made. [ABSTRACT FROM AUTHOR]

The rationale and development of a wafer-scale three-dimensional (3-D) integrated circuit technology are described. The essential elements of the 3-D technology are integrated circuit fabrication on silicon-on-insulator wafers, precision wafer-wafer alignment using an in-house-developed alignment system, low-temperature wafer-wafer bonding to transfer and stack active circuit layers, and interconnection of the circuit layers with dense-vertical connections with sub-Ω 3-D via resistances. The 3-D integration process is described as well as the properties of the four enabling technologies. The wafer-scale 3-D technology imposes constraints on the placement of the first lithographic level in a wafer-stepper process. Control of wafer distortion and wafer bow is required to achieve submicrometer vertical vias. Three-tier digital and analog 3-D circuits were designed and fabricated. The performance characteristics of a 3-D ring oscillator, a 1024 × 1024 visible imager with an 8-μm pixel pitch, and a 64 × 64 Geiger-mode laser radar chip are described. [ABSTRACT FROM AUTHOR]