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Thermal noise represents a major limitation on the performance of most electronic circuits. It is particularly important in switched circuits, such as the switched-capacitor (SC) filters widely used in mixed-mode CMOS integrated circuits. In these circuits, switching introduces a boost in the power spectral density of the thermal noise due to aliasing. Unfortunately, even though the theory of noise in SC circuits is discussed in the literature, it is very intricate. The numerical calculation of noise in switched circuits is very tedious, and requires highly sophisticated and not widely available software. The purpose of this paper is twofold. It provides a tutorial description of the physical phenomena taking place in an SC circuit while it processes noise (Sections II--III). It also proposes some specialized but highly efficient algorithms for estimating the resulting sampled noise in SC circuits, which need only simple calculations (Sections IV--VI). A practical design procedure, which follows directly from the estimate, is also described. The accuracy of the proposed estimation algorithms is verified by simulation using SpectreRF. As an example, it is applied to the estimation of the total thermal noise in a second-order low-distortion delta-sigma converter. Index Terms--Delta-sigma ([DELTA] [SIGMA]) modulator, switched-capacitor (SC) circuit, thermal noise.

Computational geometry is used to locate convex positively invariant sets for delta-sigma modulators. The existence of a positively invariant set implies the stability of the modulator and yields rigorous state bounds. Convex positively invariant sets for single-bit modulators up to order four, with a restricted class of time-varying inputs, have been found. MATLAB code implementing the proposed algorithm is available from ftp://next242.ece.orst.edu/pub/delsig.tar.Z.

Delta-sigma ([Delta][Sigma]) modulators employing continuous-time elements can be transformed to equivalent discrete-time systems. The paper derives this equivalence relation and applies it to the design of a third-order low-pass modulator and a sixth-order band-pass modulator.

Delta-sigma modulators are popular circuits for constructing high precision analog-to-digital and digital-to-analog converters. These systems contain a single nonlinear element (a quantizer) embedded in an otherwise linear system, and can exhibit such nonlinear behavior as limit cycles, subharmonics, phase-locking and chaos. Due to the discrete spectra that result when limit cycles are present, human listeners perceive objectionable tones in the quantization noise. This problem can be overcome by using dither or, as this paper suggests, by making the modulator chaotic. The effectiveness of the technique is illustrated and its impact on modulator complexity, stability, and performance is discussed.

Computer simulations are used to determine the stability limits of single-bit delta-sigma modulators up to order 8. It is found that none of the existing criteria for stability are adequate for design. Plots of the maximum signal-to-noise ratio (SNR) achievable with a given modulator order and oversampling ratio (OSR) are presented. These graphs can be used to determine the modulator order and OSR required to achieve a given SNR or to check the tightness of (as yet unavailable) theoretical bounds.

Discusses the implementation of a general purpose back-end for a narrow-band superheterodyne receiver through an integrated low-noise amplifier, mixer, bandpass sigma-delta analog-to-digital converter, decimation filter and two synthesizers. Key specification of the integrated circuit (IC); Factors that will allow the IC to be used in a variety of narrow-band applications; Evidence showing that the high dynamic range yields excellent system performance even though the power consumption is low.