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A hybrid wireless network is an extension to an infrastructure network, where a mobile host may connect to an access point (AP) using multihop wireless routes via other mobile hosts. The APs are configured to operate on one of multiple available channels. Mobile hosts and wireless routers can select their operating channels dynamically through channel switching. In this environment, we propose a routing protocol that finds routes to balance load among channels while maintaining connectivity. The protocol works with nodes equipped with a single network interface, which distinguishes our work with other multichannel routing protocols that require multiple interfaces per node. The protocol discovers multiple routes to multiple APs, possibly operating on different channels. Based on traffic load information, each node selects the 'best' route to an AP and synchronizes its channel with the AP. With this behavior, the channel load is balanced, removing hot spots and improving channel utilization. The protocol assures that every node has at least one route to an AP, where all intermediate nodes are operating on the same channel. Our simulation results show that the proposed protocol successfully adapts to changing traffic conditions and improves performance over a single-channel protocol and a multichannel protocol with no load balancing. Index Terms--Communication system routing, communication systems, load-balancing, multi-channel, multi-hop, protocols, routing.

Dominating-set-based routing in ad hoc wireless networks with unidirectional links is examined and discussed.

The concept of a restricted area for conducting message routing and balancing buffer utilization is proposed. The aim is to minimize traffic congestion.

The High-Performance Efficient Router (HiPER), a multidimensional router that accommodates high-throughput error-corrected communication channels, is discussed. HiPER combines flit-level error control and mad postman (bit-pipelined) switching.

A single, unified theory is described for design of deadlock-free fully adaptive routing algorithms for all classes of network topologies and all switching procedures. A general theory is proposed that applies to direct and indirect networks, and to regular and irregular networks.

Localized routing algorithms are discussed, which aim to minimize the total energy per packet and/or the lifetime of each node. Power consumption in static networks is a primary focus of interest.

The superiority of flooding-based methods and hybrid single-path/flooding variants, compared to LAR2, is discussed. It is shown that an approach involving loop-free, single-path algorithms and guaranteed delivery is more successful than existing procedures.

A VLSI implementation of a programmable pipelined router scheme for parallel machine interconnection networks is presented in this paper. The implementation is based on a dynamic content-addressable memory (DCAM) that supports unique bit masking per entry. The number of required DCAM entries is extremely small; it is of the same order as the node degree (output ports). This, in turn, makes it possible to implement a dynamic content-addressable memory in order to reduce the physical size of the system. A DCAM is implemented with only six and a half transistors (one transistor is shared by two cells). We have provided circuitry and arranged timing to achieve refreshing of the stored data in a hidden fashion. In addition to the DCAM, we have incorporated a fast priority scheme that allows only one entry to be selected. The router executes routing algorithms in 1.5 clock cycles, this being the fastest approach for flexible routers. The prototype router has 24 entries, and is able to sustain a throughput of one routing decision per cycle. Index Terms - Content addressable memory, dynamic circuits, matching with ternary digits, parallel comparison, pipelining, routing algorithm execution, ternary digit logic.

A previously develop model for hysteretic loss and induced magnetization bridging was extended to include metallurgical bridges' inhomogeneous morphologies. The anisotropic continuum model presented a dimensionless parameter representing the area-fraction of bridged matrix material perpendicular to the filamentary axis. The parameters were then used to describe the bridging intensity.

An object-oriented discrete-event simulation environment, pp-mess-sim, acts as a flexible and extensible simulator that evaluates multicomputer networks in message-passing systems. The simulation environment pp-mess-sim is capable of analyzing various network topologies, routing-switching policies, and router models, under different levels of communication workload. The object-oriented pp-mess-sim simulates computer networks that can handle multiple routing and switching schemes simultaneously, by correlating routing-switching policies and traffic patterns with collections of packets.

An associative approach involving the mapping of algorithms onto a set of bit-patterns, matched in parallel, provides flexibility and quick execution for implicit routing algorithms. The mapping of a large number of routing algorithms for a broad range of interconnection network topologies indicates that the number of required bit-patterns and the topology degree are of the same order. The hardware requirement for the scheme is low. Three cases showing the capabilities of the router approach are discussed.

In this paper the low frequency harmonic distortion of the mains current of a three-phase single-switch discontinuous-mode boost-rectifier is calculated. The system analysis is based on application of space vector calculus and on substitution of discontinuous time shapes within a pulse period by quasicontinuous time shapes. The quasicontinuous time shapes are defined by averaging over the pulse period. The dependency of the shape of the input currents on the voltage transformation ratio is given for various control methods in analytical form. The results of the theoretical analysis are verified by digital simulation and by measurements on a laboratory model. A good consistency of the results has been found.

The hot potato algorithms are asymptotically optimal for the two-dimensional grid and torus. An O(n squared) hot potato algorithm analyzes the n-dimensional Boolean equation. The algorithm produces three time bounds for permutation routing. A complexity of o(2 to the nth power) steps was attained for the first time by the deterministic algorithm for the 2 raised to the nth power -nodes Boolean cube. The experimental procedure for the development of algorithm is discussed.

This paper describes the effect of supply voltage harmonics on the response of single-phase capacitor-filtered diode bridge rectifier loads. A complete analytical model for calculating the current harmonics of these loads, when energized by nonsinusoidal supply voltages, is presented. The model is then used to investigate the effect of supply voltage harmonics on current harmonics. The key findings of the paper are as follows: 1. The phase angles of supply voltage harmonics determine whether or not these harmonics increase or decrease current distortion. In general, a peaked voltage wave increases input current distortion, whereas a flattened wave has the opposite affect. Because of this complex relationship, voltage crest factor is a much better predictor of total harmonic current distortion (THDI) than is total harmonic voltage distortion (THDV). 2. The current harmonics created by these loads produce voltage harmonics that tend to have a partial self-compensating effect on the current harmonics. Keywords - Single-phase diode bridge rectifier, input current harmonics, nonsinusoidal supply voltage, voltage crest factor.

Current-voltage measurements are performed to determine whether large current sensitivities can be obtained in high temperature superconductive YBCO MgO microbridges as a function of temperature. The experiments are performed using a superconducting microbridge as a sensor and a commercial regulator. Results suggest that the temperature of the microbridges can be regulated to improve their dynamic resistance and make the phonon noise more dominant.

An optimal broadcast algorithm developed for dealing with broadcasting problems in hypercubes includes wormhole, e-cube routing and all-port communication. The algorithm involves only O(n/log to the base 2 (n + 1)) wormhole routing steps. Simple recursive functions illustrated in pseudocodes are capable of representing the algorithm. Specific upper and lower bounds for n less than or equal to 10 help enhance the (n/2) upper bound.

A novel system obtaining very low distorted waveforms of input ac currents of three-phase rectifier circuits are proposed. The proposed rectifier system consists of a three-phase diode bridge circuit as a main power circuit, ac reactors, and an additional circuit which serves as an active filter with low switching frequencies and a forced-commutation circuit for the diodes. This paper describes the operation principle, analysis of the waveforms of input voltage and current, multiple phase-shifted systems, and the experimental results. The proposed system gives excellent input current waveforms and has many advantages over conventional systems.

In order to reduce interconnection delay and increase packaging density, the multichip module (MCM) technology is used in the design of high-performance VLSI systems. A commonly used method for multilayer MCM designs is the three-dimensional (3-D) maze routing, which suffers from a number of problems: it is very sensitive to the net ordering, it requires long computation time, and it often results in a large number of vias in the routing solutions. The objective of this research is to develop an efficient multilayer general area router as an alternative to the 3-D maze router for solving the multilayer MCM routing problem. Our router, named SLICE, is independent of net ordering, requires much shorter computation time, and uses fewer vias. A key step in our router is to compute a maximum noncrossing bipartite matching, which is solved optimally in O(n log n) time where n is the number of possible connections. We tested our router on a number of examples, including two MCM designs from MCC. The total wirelength used by SLICE is only a few percent away from the optimal on average. Compared with a 3-D maze router, SLICE is six times faster and uses 29% fewer vias. Another feature of SLICE is that it works on only a 'thin slice' of a two-layer routing grid at a time, while a 3-D maze router works on the entire 3-D routing grid. Therefore, SLICE can successfully produce solutions for large MCM routing examples where 3-D maze routers fail due to insufficient memory.

In the design of high performance VLSI systems, minimization of clock skew is an increasingly important objective. Additionally, wirelength of clock routing trees should be minimized in order to reduce system power requirements and deformation of the clock pulse at the synchronizing elements of the system. In this paper, we first present the deferred-merge embedding (DME) algorithm, which embeds any given connection topology to create a clock tree with zero skew while minimizing total wirelength. The algorithm always yields exact zero skew trees with respect to the appropriate delay model. Experimental results show an 8% to 15% wirelength reduction over previous constructions in (17) and (18). The DME algorithm may be applied to either the Elmore or linear delay model, and yields optimal total wirelength for linear delay. DME is a very fast algorithm, running in time linear in the number of synchronizing elements. We also present a unified BB + DME algorithm, which constructs a clock tree topology using a top-down balanced bipartition (BB) approach, and then applies DME to that topology. Our experimental results indicate that both the topology generation and embedding components of our methodology are necessary for effective clock tree construction. The BB + DME method averages 15% wirelength savings over the previous method of (17), and also gives 10% average wirelength savings when compared to the method of (25). The paper concludes with a number of extensions and directions for future research.

A network-partitioning approach for one-to-all broadcasting on wormhole routed networks was proposed. This was based on constructing multiple independent subnetworks which can work concurrently to increase the parallelism in communication. It was distinguished from the traditional edge-disjoint-spanning-trees-based approach. Its application to tori, meshes and hypercubes was described.

A general theoretical framework for the analysis of deadlock-free routing functions is described. The theory captures most of the definitions of a routing function which include vertex-dependent, source-dependent, path-dependent and input-dependent. Its application is not restricted to one-to-one routing that selects the output channel as a function of the current node or the current input channel but also to one-to-many routing.