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In H.264/AVC intra-frame coding, the rate-distortion optimization (RDO) is employed to select the optimal coding mode to achieve the minimum rate-distortion cost. Due to a large number of combinations of coding modes, the computational burden becomes extremely high in intra-prediction. In this paper, we propose two fast, efficient but reliable direction detection algorithms by computing subblock and pixel direction differences. Both proposed methods effectively estimate the edge direction inside the block to narrow down the predictive modes to reduce the RDO computation. Experimental results show that the proposed methods can reduce the encoding time by about 60% with negligible loss of coding performance. For hardware realization, a fast mode decision VLSI circuit for intra-prediction with the silicon core size of 0.12 x 0.12 [mm.sup.2] at 0.18-[micro]m CMOS technology is implemented. The fast mode decision VLSI in three-stage pipelined architecture operated at 173 MHz can encode 30 fps real-time videos up to Level 5. Index Terms--Edge direction detection, H264/AVC, intraprediction, Joint Video Team (JVT), rate-distortion (RD) optimization.

In this paper, a new subspace-based speech enhancement model is presented for in-car speech enhancement. To effectively suppress background noise, this model incorporates a perceptual filterbank and an auditory gain adaptation derived from a psychoacoustic model into a signal subspace approach. The projection approximation subspace tracking deflation (PASTd) algorithm is used to track the signal subspace. For real-time processing, a system-on-a-programmable-chip architecture and a very large scale integration design of the PASTd algorithm are proposed. To realize a pipeline computation, this paper presents a pipelined PASTd architecture without data-dependent hazards. The maximum clock rate is 9.7 MHz, and the typical clock rate, which achieves the real-time requirement, is 4.6 MHz. The corresponding architecture was experimentally verified via an ALTERA EPXA10 development board. Index Terms--In-car noise, psychoacoustic model (PAM), speech enhancement, subspace tracking, system-on-a-programmable-chip (SoPC).

This study presents an intensity gradient approach for intra-prediction in H.264 encoding system, which enhances the performance and efficiency of previous fast algorithms. We propose a preprocessing stage in which eight orientation features are extracted from a macro block by the intensity gradient filters. The orientation features are utilized to select a subset of prediction modes to be involved in the rate-distortion calculation so that the encoding time can be reduced. The simulation results indicate that the intensity gradient based algorithm for intra-prediction contributes better tradeoff between rate-distorion performance and encoding complexity than the previous algorithms. Compared to H.264 reference software, the proposed algorithm introduces slight PSNR degradation and bit rate increase but saves around 76 % of the total encoding time with all intra-frame coding. Index Terms--H.264, intensity gradient, intra-prediction, orientation, rate distortion.

In this paper, we present a fast mode decision algorithm and design its VLSI architecture for H.264 intra-prediction. A regular spatial domain filtering technique is proposed to compute the dominant edge strength (DES) to reduce the possible predictive modes. Experimental results revealed that the proposed fast intra-algorithm reduces 40% computation with slight peak signal-to-noise ratio (PSNR) degradation. The designed DES VLSI engine comprises a zigzag converter, a DES finite-state machine (FSM), and a DES core. The former two units handle memory allocation and control flow while the last performs pseudoblock computation, edge filtering, and dominant edge strength extraction. With semicustom design fabricated by 0.18-/[micro]m CMOS single-poly-six-metal technology, the realized die size is roughly 0.15 x 0.15 [mm.sup.2] and can be operated at 66 MHz. Index Terms--Advanced video coding (AVC), dominant edge extraction, H264, intra-mode decision, intra-prediction.

Previous research shows that there are two architectures for spoken language translation (SLT) system implementation. One is client-server based systems that should be built on the server computer but unreliability of the remote connection. The other is to build portable stand-alone devices but it lacks real-time performance. In this brief, a system-on-a-programmable-chip (SoPC) solution is proposed by realizing the entire SLT system within a single chip. This SoPC is characterized by small size, low cost, real-time operation, and high portability. This entire design was implemented on ALTERA EPXA10 device. Performance for English-to-Mandarin translation process can be completed within 1 s at a 46.22-MHz clock frequency with 3000 translation patterns. The total logic usage of the EPXA10 device is 50% (about 19318 logic cells). Index Terms--ARM, language translation, system-on-a-programmable-chip (SoPC), speech processing, speech recognition.

The dynamic Huffman encoding procedure hinders the encoding break problem arising due to interference, to execute the tree-tuning and the code generation processes concurrently. This saves about 45% of the steps in the sequential approach. The concurrent hardware method gives an output rate of 1 bit per step for dynamic Huffman encoding, which is same as that of tree-based static Huffman encoding.

This paper presents an efficient pipeline architecture to perform gray-scale morphologic operations. The features of the architecture are 1) lower hardware cost, 2) faster operation time in processing an image. 3) lower data access times from the image memory, 4) shorter latency, 5) suitability for VLSI implementation, and 6) adaptability for N*N morphologic operations.

in interframe video coding, the three-step search (TSS) method is often used for motion estimation, largely due to its simplicity. However, the TSS method sometimes may produce ambiguous search directions and terminate the search at a local minimum. In this paper, techniques to improve the performance of the TSS method are presented., The dynamic search-window adjustmentmethod and the interlaced-search approach were combined to form an algorithm for enhancing the motion estimation operation of the three-step search algorithm. The proposed scheme demonstrated reduced computational complexity and lower displaced frame difference in experiments evaluating its performance against other fast search algorithms.