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(VFB) monitoring using optical-substrate-current spectroscopy (ISub,photo spectroscopy) in nitride-based charge-trap Flash (CTF) memories is proposed. Under optical illumination by photons with above-bandgap energy Eph(> Eg,Si), ISub,photo is abruptly increased at the gate voltage VG = VFB due to a sudden increase of the excess minority-carrier diffusion current. As expected ,in this principle, while the single-step feature of the ISub,photo--VG curve is observed in the case of N-MOSFETs, a multistep response is clearly observed in nitride-based CTF memories. The mechanism of steplike ISub,photo spectroscopy is analyzed, supported by analytical models, and verified by comparison with TCAD simulation results. The results show that the height of the step corresponds to the lateral length LTC of the region, over which localized trapped charges are distributed, and its width to the density Qnit (x) = qNnit (x) [C/cm2] in the nitride storage layer. Based on the proposed ISub,photo spectroscopy, lateral charge profiling is demonstrated in a programmed NROM cell. The validity of the proposed ISub,photo spectroscopy is confirmed by comparing the measured ID-VG characteristics with TCAD simulation incorporating the extracted Nnit(x) by ISub,photo spectroscopy. The proposed lateral charge-profiling technique is expectedto be a useful technique for extracting the trapped-charge distribution in NROM and/or multibit CTF memories. This extraction technique has advantages of electrical stress free, exclusion of the effect from interface traps, and the applicability to devices with large gate leakage current. [ABSTRACT FROM AUTHOR]

Studies silicon single-electron transistors (SET) with sidewall depletion gates and their application to dynamic single-electron transistor logic. Device characteristics immune to the gate bias condition; Significance of SET; Feasibility of the dynamic four-input multifunctional SET logic circuit.

Charge spreading behavior within a few seconds, referred to as early retention, was comprehensively investigated in 24 word-line stacked tube-type 3D NAND flash memory. We thoroughly explored the charge spreading behavior from the perspectives of both electron and hole spreading in 3D NAND flash memory with different charge trap layer thicknesses at various programming and erasing levels for solid and checkerboard patterns to provide guidelines for minimizing and optimizing the charge spreading. [ABSTRACT FROM AUTHOR]