1. Efficient Hardware Architecture of \etaT Pairing Accelerator Over Characteristic Three.
- Author
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Chung, Szu-Chi, Fu, Hsing-Ping, Wu, Jing-Yu, Lee, Chen-Yi, Chang, Hsie-Chia, and Lee, Jen-Wei
- Subjects
APPLICATION-specific integrated circuit design & construction ,COMPLEMENTARY metal oxide semiconductors ,ELLIPTIC curve cryptography ,DATA encryption ,EXPONENTIATION ,CLOUD computing - Abstract
To support emerging pairing-based protocols related to cloud computing, an efficient algorithm/hardware codesign methodology of \etaT pairing over characteristic three is presented. By mathematical manipulation and hardware scheduling, a single Miller's loop can be executed within 17 clock cycles. Furthermore, we employ torus representation and exploit the Frobenius map to lower the computation cost of final exponentiation. Pipelining and parallelization datapath are also exploited to shorten the critical path delay. Finally, by choosing suitable multiplier architecture and selecting an appropriate number of multipliers, Miller's loop and final exponentiation can be computed in a fully pipelined manner. With these schemes, a test chip for the proposed pairing accelerator has been fabricated in 90-nm CMOS 1P9M technology with a core area of 1.52 \,\times\, 0.97 {\rm mm}^{2} . It performs a bilinear pairing computation over F(3^{97}) in 4.76 \mus under 1.0 V supply and achieves 178% improvement to relative works in terms of area–time (AT) product. To support higher level of security, a 126-bit secure pairing accelerator that can complete a bilinear pairing computation over F(3^709) in 36.2 \mus is implemented and this result is at least 31% better than relative works in terms of AT product. [ABSTRACT FROM PUBLISHER]
- Published
- 2015
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