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Smart healthcare systems integrated with advanced deep neural networks enable real‐time health monitoring, early disease detection, and personalized treatment. In this work, a novel 3D AND‐type flash memory array with a rounded double channel for computing‐in‐memory (CIM) architecture to overcome the limitations of conventional smart healthcare systems: the necessity of high area and energy efficiency while maintaining high classification accuracy is proposed. The fabricated array, characterized by low‐power operations and high scalability with double independent channels per floor, exhibits enhanced cell density and energy efficiency while effectively emulating the features of biological synapses. The CIM architecture leveraging the fabricated array achieves high classification accuracy (93.5%) for electrocardiogram signals, ensuring timely detection of potentially life‐threatening arrhythmias. Incorporated with a simplified spike‐timing‐dependent plasticity learning rule, the CIM architecture is suitable for robust, area‐ and energy‐efficient in‐memory arrhythmia detection systems. This work effectively addresses the challenges of conventional smart healthcare systems, paving the way for a more refined healthcare paradigm. [ABSTRACT FROM AUTHOR]

There is a need to design a hardware synapse array appropriate for enhancing the efficiency of neuromorphic computing systems while minimizing energy consumption. This study introduces a memristor device with an AlOx overshoot suppression layer (A‐OSL) to achieve a self‐compliance effect. By optimizing each cell within the 16 × 16 crossbar array, synaptic devices are successfully fabricated with reliable characteristics and 3‐bit multilevel capabilities. In addition, the oxygen composition of TiOx and the annealing conditions are optimized to reduce the forming voltage and minimize the variation in the switching voltage. As a result, stable forming‐free characteristics are obtained through A‐OSL insertion, a reduction in forming voltage, and TiOx oxygen composition optimization. Also, target weights are accurately transferred to the A‐OSL memristor crossbar array and conducted the inference process by applying spike signals to the array following the designated time step. The spiking neural network (SNN) is demonstrated by measuring vector‐matrix multiplication (VMM) of the 16 × 16 crossbar array. The VMM results exhibit a classification accuracy of 90.80% for the MNIST dataset, which is close to the accuracy achieved by software‐based approaches, amounting to 91.85%. [ABSTRACT FROM AUTHOR]

Herein, dual‐gate field‐effect transistors (DG FETs) fabricated on Si substrate and a corresponding NOR‐type array designed for low‐power on‐chip trainable hardware neural networks (HNNs) are presented. The fabricated DG FET exhibits notable endurance characteristics, with the subthreshold swing remaining consistently within a 2.45% range of change and ΔVth per cycle maintaining stability at 4.5% over repetitive program and erase operations, up to 104 cycles. Furthermore, a multilevel characteristic is achieved through low‐power program/erase operations based on Fowler–Nordheim (FN) tunneling, which exhibit 0.09 and 0.99 fJ per spike, respectively. These characteristics provide the HNN stability, along with high performance and power efficiency. The NOR‐type array in this work demonstrates selective update and bidirectional vector‐by‐matrix multiplication capabilities. This enables on‐chip training based on a gradient descent algorithm, without the need for an additional array for backpropagation. Subsequently, a simulation of the Modified National Institute of Standards and Technology classification is conducted to evaluate the accuracy and training power consumption of the proposed device in comparison to other two‐terminal memristor devices. The results show that the DG FET array achieves superior accuracy while maintaining over 180.4 times higher energy efficiency, demonstrating the potential of the DG FET as a promising candidate for low‐power HNN applications. [ABSTRACT FROM AUTHOR]

The application of nanoelectromechanical (NEM) memory switches to field-programmable gate arrays (FPGAs) has been proposed for the first time. NEM memory switches replace MOSFETs and NEM relay switches in connection blocks and switch boxes. The proposed NEM-memory-based FPGAs feature higher speed, lower energy consumption, and smaller chip area than the other FPGAs. In addition, compared with the previously reported NEM-relay-based FPGAs, they show nonvolatile storage of signal paths and stable rail-to-rail signal voltage swing because data signal paths are maintained by adhesion force. In addition, the contact resistance ( \boldsymbol R co ) of a NEM memory switch is lower than that of a NEM relay switch thanks to larger contact area. [ABSTRACT FROM AUTHOR]

This paper proposes a high-efficiency isolated bridgeless single-ended primary inductor converter (SEPIC) for light-emitting-diode (LED) displays. The proposed isolated SEPIC converter can supply LED back-light power with reduced conduction losses. Switching power losses as well as conduction losses are reduced. The proposed converter is theoretically analysed. Experimental results based on a 28 V, 300 W back-light power are discussed to verify the performance of the proposed converter. [ABSTRACT FROM AUTHOR]

This paper proposes a high-efficiency dc–dc converter with fast dynamic response for low-voltage photovoltaic (PV) sources. The voltage stress of power switches is reduced at low-voltage side. Zero-current turn-off of output diodes is achieved at high-voltage side. Power efficiency is improved by reducing switching power losses. A modified proportional and integral controller is also suggested to achieve fast output voltage control. The dynamic response of the proposed converter is improved. The performance of the proposed converter is verified based on an experimental prototype for a 200-W PV module. [ABSTRACT FROM AUTHOR]

In this article, a multiple switching-mode series-resonant half-bridge (SRHB) dc–dc converter is presented. The proposed multiple switching scheme changes switching modes to improve power efficiency for a wide output range, especially in the low output power range. This multiple switching scheme is composed of three different switching modes depending on the output power. The prototype was implemented using a single-chip microcontroller. With the multiple switching mode, high efficiency is achieved over an entire output power region. Experimental results on a 1.2 kW prototype are presented to confirm the performance of the proposed multiple switching scheme for an SRHB converter. [ABSTRACT FROM AUTHOR]

Abstract: This paper presents a high-efficiency grid-connected photovoltaic (PV) module integrated converter (MIC) system with reduced PV current variation. The proposed PV MIC system consists of a high-efficiency step-up DC–DC converter and a single-phase full-bridge DC–AC inverter. An active-clamping flyback converter with a voltage-doubler rectifier is proposed for the step-up DC–DC converter. The proposed step-up DC–DC converter reduces the switching losses by eliminating the reverse-recovery current of the output rectifying diodes. To reduce the PV current variation introduced by the grid-connected inverter, a PV current variation reduction method is also suggested. The suggested PV current variation reduction method reduces the PV current variation without any additional components. Moreover, for centralized power control of distributed PV MIC systems, a PV power control scheme with both a central control level and a local control level is presented. The central PV power control level controls the whole power production by sending out reference power signals to each individual PV MIC system. The proposed step-up DC–DC converter achieves a high-efficiency of 97.5% at 260W output power to generate the DC-link voltage of 350V from the PV voltage of 36.1V. The PV MIC system including the DC–DC converter and the DC–AC inverter achieves a high-efficiency of 95% with the PV current ripple less than 3% variation of the rated PV current. [Copyright &y& Elsevier]

Embedded processors are widely used in various systems working on different tasks with different workloads. A more complex micro-architecture leads to better peak performance and worse power consumption. Shutting down the units designed for performance enhancement could improve energy efficiency in low-workload scenarios. In this paper, we evaluated the energy distribution in various embedded processors. According to the analysis, pipeline registers and the dynamic branch predictor, which are employed for better peak performance, have great impacts on energy efficiency. Thus, we proposed an ultra-low-power processor with variable micro-architecture. The processor is based on a 4-stage pipeline core with a Gshare branch predictor, and all units work in high-performance mode. In normal mode, the Gshare predictor is shut down and Always-Not-Taken prediction is used. In low-power mode, some of the pipeline registers are bypassed to avoid unnecessary energy dissipation and improve executing efficiency. A mode register (MR) is designed to indicate current working mode. Switching between different modes is controlled by the software. The proposed core is implemented in 40 nm technology and simulated with the traces of 17 benchmarks in Embench. The average amounts of power consumed by the respective modes are 41.7 μW, 59.7 μW and 71.1 μW. The results show that normal mode (N-mode) and low-power mode (L-mode) consume 16.08% and 41.37% less power than high-performance mode (H-mode) on average. In best case scenarios, they could save 25.36% and 49.30% more power than H-mode. Considering the execution efficiency evaluated by instructions per cycle (IPC), the proposed processor consumes 7.78% or 51.57% less energy for each instruction than the baseline core. The area of the proposed processor is only 7.19% larger than the baseline core, and only 3.08% more power is consumed in H-mode. [ABSTRACT FROM AUTHOR]

The work-function variation (WFV) effects of tunneling field-effect transistors (TFETs) are discussed for the first time. According to the 3-D device simulation results, TFETs are less immune to the WFV than metal–oxide–semiconductor FETs (MOSFETs) in terms of subthreshold swing (S) and threshold voltage (Vth). TFETs show \sim1.4\times larger Vth standard deviation (\sigma Vth) and \sim4.6\times larger S standard deviation (\sigma S) than MOSFETs at high drain voltage (VD). It is because TFET characteristics are mainly determined by WF values of metal grains near to the source region where band-to-band tunneling occurs. [ABSTRACT FROM PUBLISHER]

The zeta inverter has been used for single-phase grid-tied applications. For its use of energy storage systems, this paper proposes the bidirectional operation scheme of the grid-tied zeta inverter. A shoot-through switching state is introduced, providing reliable bidirectional operation modes. A shoot-through duty cycle is utilized for the bidirectional grid current control of the inverter. The grid current is bidirectionally controlled by the shoot-through duty cycle, which enables the inverter to operate with seamless change of operation modes. Over the state-of-the art techniques using flyback and Cuk inverter topologies, the grid-tied zeta inverter using the proposed operation scheme provides advantages of high efficiency, low cost, and high reliability. The operation principle is presented by describing the operation mode and control method for the grid-tied zeta inverter. A 500 W prototype has been built and tested to verify its operation principle. [ABSTRACT FROM AUTHOR]