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The primary contributors to elevated line losses in low-voltage distribution networks are three-phase load imbalances and variations in load peak–valley differentials. The conventional manual phase sequence adjustment fails to capitalize on the temporal characteristics of the load, and the proliferation of smart homes has opened up new scheduling possibilities for managing the load. Consequently, this paper introduces a loss-reduction method for low-voltage distribution networks that leverages load-timing characteristics and adjustment capabilities. This method combines dynamic and static methods to reduce energy consumption from different time scales. To commence, this paper introduced a hierarchical fuzzy C-means algorithm (H-FCM), taking into account the distance and similarity of load curves. Subsequently, a phase sequence adjustment method, grounded in load-timing characteristics, was developed. The typical user load curve, derived from the classification of user loads, serves as the foundation for constructing a long-term commutation model, therefore mitigating the impact of load fluctuations on artificial commutation. Following this, this paper addressed the interruptible and transferable characteristics of various smart homes. This paper proposed a multi-objective transferable load (TL) optimal timing task adjustment model and a peak-shaving control strategy specifically designed for maximum sustainable power reduction of temperature-controlled loads (TCL). These strategies aim to achieve real-time load adjustment, correct static commutation errors, and reduce peak-to-valley differences. Finally, a simulation verification model was established in MATLAB (R2022a). The results show that the proposed method mainly solves the problems of three-phase imbalance and large load peak–valley difference in low-voltage distribution networks and reduces the line loss of low-voltage distribution networks through manual commutation and load adjustment. [ABSTRACT FROM AUTHOR]

Recent years have seen a rapid rise of artificial neural networks being employed in a number of cognitive tasks. The ever‐increasing computing requirements of these structures have contributed to a desire for novel technologies and paradigms, including memristor‐based hardware accelerators. Solutions based on memristive crossbars and analog data processing promise to improve the overall energy efficiency. However, memristor nonidealities can lead to the degradation of neural network accuracy, while the attempts to mitigate these negative effects often introduce design trade‐offs, such as those between power and reliability. In this work, authors design nonideality‐aware training of memristor‐based neural networks capable of dealing with the most common device nonidealities. The feasibility of using high‐resistance devices that exhibit high I‐V nonlinearity is demonstrated—by analyzing experimental data and employing nonideality‐aware training, it is estimated that the energy efficiency of memristive vector‐matrix multipliers is improved by almost three orders of magnitude (0.715 TOPs−1W−1 to 381 TOPs−1W−1) while maintaining similar accuracy. It is shown that associating the parameters of neural networks with individual memristors allows to bias these devices toward less conductive states through regularization of the corresponding optimization problem, while modifying the validation procedure leads to more reliable estimates of performance. The authors demonstrate the universality and robustness of this approach when dealing with a wide range of nonidealities. [ABSTRACT FROM AUTHOR]

Research has shown that deep neural networks contain significant redundancy, and thus that high classification accuracy can be achieved even when weights and activations are quantized down to binary values. Network binarization on FPGAs greatly increases area efficiency by replacing resource-hungry multipliers with lightweight XNOR gates. However, an FPGA's fundamental building block, the $K$ K -LUT, is capable of implementing far more than an XNOR: it can perform any $K$ K -input Boolean operation. Inspired by this observation, we propose LUTNet, an end-to-end hardware-software framework for the construction of area-efficient FPGA-based neural network accelerators using the native LUTs as inference operators. We describe the realization of both unrolled and tiled LUTNet architectures, with the latter facilitating smaller, less power-hungry deployment over the former while sacrificing area and energy efficiency along with throughput. For both varieties, we demonstrate that the exploitation of LUT flexibility allows for far heavier pruning than possible in prior works, resulting in significant area savings while achieving comparable accuracy. Against the state-of-the-art binarized neural network implementation, we achieve up to twice the area efficiency for several standard network models when inferencing popular datasets. We also demonstrate that even greater energy efficiency improvements are obtainable. [ABSTRACT FROM AUTHOR]