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GaN-on-Si high-electron-mobility transistors (HEMTs) exhibit excellent properties for efficient power conversion. Nevertheless, a considerable energy loss associated with the charging and discharging of the output capacitance (COSS) in these transistors severely limits their application at high switching frequencies. In this work we report the observation of unexpected resonances in GaN-on-Si HEMTs. These high-frequency resonances lead to considerable energy losses in fast charging and discharging of the COSS during switching transients. We propose a simple wafer-level measurement technique to evaluate such losses at the epitaxy level, prior to the transistor fabrication. Experimental results from this technique revealed that the Silicon substrate is the main origin of these losses. Such wafer-level evaluation of COSS losses opens opportunities to characterize and optimize epitaxies for future power devices, especially those operating at high switching frequencies. [ABSTRACT FROM AUTHOR]

Soft-switching power converters based on wide-band-gap (WBG) transistors offer superior efficiency and power density advantages. However, at high frequencies, loss behavior varies significantly between different WBG technologies. This includes losses related to conduction and dynamic on-state resistance (RDS(ON)) degradation, also charging/discharging of input capacitance (CISS) and output capacitance (COSS). As datasheets lack such important information, we present measurement techniques and evaluation methods for soft-switching losses in WBG transistors which enable a detailed loss-breakdown analysis. We estimate the gate loss under soft-switching conditions using a simple small-signal measurement. Next, we use Sawyer–Tower and nonlinear resonance (NR) methods to measure large-signal COSS energy losses up to 40 MHz. Finally, we investigate the dependence of dynamic RDS(ON) degradation on off-state voltage using pulsed-IV measurements. We demonstrate an insightful comparison of soft-switching losses for various normally off gallium nitride (GaN) and silicon carbide (SiC) devices. A p-GaN-gated device exhibits the most severe RDS(ON) degradation and the lowest gate loss. Cascode arrangement increases threshold voltage for GaN devices and reduces gate losses in SiC transistors; however, it leads to higher C{OSS losses. The study facilitates the evaluation of system losses and selection of efficient WBG devices based on the trade-offs between various sources of losses at high frequencies. [ABSTRACT FROM AUTHOR]

The low on-resistance of wide-band-gap (WBG) transistors is a key feature for efficient power converters; however, the anomalous loss in their output capacitance (COSS) severely limits their performance at high switching frequencies. Characterizing COSS losses based on the large-signal measurement methods requires an extensive effort, as separate measurements are needed at different operation points, including voltage swing, frequency, and dv/dt. Furthermore, there is a practical tradeoff in the maximum voltage and frequency applied to the device. Here, we introduce a new circuit model, including an effective COSS and a frequency-dependent series resistance, along with a simple small-signal method to fully characterize COSS losses in WBG transistors. The method accurately predicts COSS losses at any voltage swing or frequency. Contrary to other methods, this technique directly leads to a general identification of COSS losses at different operation points, revealing new insights on COSS losses in WBG transistors, especially the dependence of EDISS on voltage and frequency. Based on the proposed approach, the issue of COSS losses in enhancement-mode GaN and SiC transistors was assigned to the limited quality factor of COSS. The precise characterization of COSS losses proposed in this letter is essential for designing efficient high-frequency power converters. [ABSTRACT FROM AUTHOR]

In this letter, we present a new measurement technique to evaluate the large-signal output capacitance (COSS) of transistors as well as the COSS energy dissipation (EDISS), based on the nonlinear resonance between a known inductor and the output capacitance of the device under test. The method is simple and robust, and only requires a single voltage measurement to extract the large-signal COSS both in charging and discharging transients. By changing the circuit parameters, it is possible to tune the resonance frequency (even above 40 MHz) and the voltage swing (even above 1 kV) with dv/dt exceeding 100 V/ns, even though the method relies only on a low-voltage dc source, without the need for high-voltage RF amplifiers. The single-pulse operation of the method enables measuring COSS and EDISS at very high frequency and dv/dt values without any thermal runaway. Using the proposed method, we extracted large-signal COSS and EDISS of power transistors based on different semiconductor technologies. The obtained results were verified by Sawyer–Tower method and data reported in the literature. In particular, dv/dt-independent COSS losses were measured in cascode GaN transistors. The precise characterization of large-signal COSS of transistors presented in this letter is essential for the design of power converters, especially those operating at high switching frequencies. [ABSTRACT FROM AUTHOR]