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As the fabrication technology goes beyond nano-scale, the VLSI layout design using Complementary Metal Oxide Semiconductor (CMOS) becomes obsolete due to its short channel effects and leakage currents. Quantum-dot Cellular Automata (QCA) is a novel paradigm proposed to overcome the drawbacks of CMOS circuits at nano-scale. Complex arithmetical operations need accurate and fast computing architectures. Though performing arithmetical operations on fixed-point numbers is easy, however, floating-point numbers have significant advantages. Moreover, the operations on floating-point numbers decide the speed and accuracy of the arithmetic unit. Hence, it is crucial to design a precise computing architecture for floating-point numbers. This paper presents for the first time an optimized architecture using QCA technology for the addition of single-precision floating-point numbers. The proposed model has been designed with lesser number of blocks which have been proved to be the best among the existing models. The proposed floating-point adder is simulated using QCADesigner tool that requires 10,370 quantum cells in an area of 21.25 μm2 with a delay of 15 clock cycles. The energy dissipation analysis of proposed architecture is studied using QCA Designer-E tool based on which the power dissipation is also calculated. The proposed model has a power dissipation of 6.56 nW, which is an improvement of 98% compared to present CMOS technology. [ABSTRACT FROM AUTHOR]

Comparator is an essential building block in many digital circuits such as biometric authentication, data sorting, and exponents comparison in floating-point architectures among others. Quantum-dot Cellular Automata (QCA) is a latest nanotechnology that overcomes the drawbacks of Complementary Metal Oxide Semiconductor (CMOS) technology. In this paper, novel area optimized 2n-bit comparator architecture is proposed. To achieve the objective, 1-bit stack-type and 4-bit tree-based stack-type (TB-ST) comparators are proposed using QCA. Then, two tree-based architectures of 4-bit comparators are arranged in two layers to optimize the number of quantum cells and area of an 8-bit comparator. Thus, this design can be extended to any 2n-bit comparator. Simulation results of 4-bit and 8-bit comparators using QCADesigner 2.0.3 show that there is a significant improvement in the number of quantum cells and area occupancy. The proposed TB-ST 8-bit comparator uses 2.5 clock cycles and 622 quantum cells with area occupancy of 0.49 µm2 which is an improvement by 10.5% and 38%, respectively, compared to existing designs. Scaling it to a 32-bit comparator, the proposed architecture requires only 2675 quantum cells in an area of 2.05 µm2 with a delay of 3.5 clock cycles, indicating 9.35% and 28.8% improvements, respectively, demonstrating the merit of the proposed architecture. Besides, energy dissipation analysis of the proposed TB-ST 8-bit comparator is simulated on QCADesigner-E tool, indicating average energy dissipation reduction of 17.3% compared to existing works. [ABSTRACT FROM AUTHOR]