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Author(s): CHEN, LEE-HUANG | Advisor(s): Agogino, Alice M. | Abstract: This dissertation presents the design, analysis and testing of various actuated modular spherical tensegrity robots for co-robotic and space exploration applications. Tensegrity structures are of interest in the field of soft robotics due to their flexible and robust nature. They have the ability to passively distribute forces globally providing shock protection from unexpected impact forces. This feature makes them a robust mobile platform suitable for uneven terrain and unpredictable environments in which traditional robots struggle. Robots built from tensegrity structures, which are composed of pure tensile and compression elements, have many potential benefits including high robustness through redundancy, many degrees of freedom in movement and flexible design. However, to fully take advantage of these properties a significant fraction of the tensile elements should be actuated, leading to a potential increase in complexity, messy cable and power routing systems and increased design difficulty.The first part of this dissertation presents an elegant solution to a fully actuated tensegrity robot: the TT-3 (version three) tensegrity robot was developed at University of California Berkeley, in collaboration with NASA Ames. The TT-3 is a lightweight, low cost, modular, and rapidly prototyped spherical tensegrity robot. This dissertation describes in detail the novel design mechanisms, architecture and simulations of TT-3, the first untethered, fully actuated cable-driven six-bar tensegrity spherical robot ever built and tested for mobility. Furthermore, this dissertation discusses the controls and preliminary testing performed to observe TT-3’s system behavior and performance and was evaluated against previous models of tensegrity robots developed at University of California at Berkeley and elsewhere.The second part of this dissertation will present a new platform for prototyping spherical tensegrity robots that significantly reduces the time required for manufacturing and assembly. This simplified tensegrity system design allows for more scientific experiments to be performed in less time. This work describes the design architecture of the TT-4mini, an example of a robot that uses this prototyping platform. In order to demonstrate the platform’s use for scientific experiments, the TT-4mini was shown to achieve uphill climbing, which has not been performed by any other spherical tensegrity robot in hardware. This dissertation discusses preliminary observations on the system’s performance in uphill climbing from simulations and testing, including evidence of climbing surfaces with an incline up to 13 degrees. Furthermore, this new prototyping platform demonstrated the ability to create three complex 12-bar tensegrity structures with simplified procedures.Lastly, the dissertation presents the improved tensegrity robot using the rod-centered architecture: the TT-4 (version four). It is a larger robot; its rod length is 1 meter compared to the 0.65 meter rod length of TT-3. The goal of the TT-4 robot prototype is twofold: to evaluate both the design improvements and the interaction of the robot with a center payload. Because the size of the robot has increased, the volume at the center of the robot available to hold payload has also increased. This allows researchers to further study the configuration, method of attachment, and the dynamics of a payload.These robots are based on a ball-shaped six-bar tensegrity structure and features a unique modular rod-centered distributed actuation and control architecture. This revolutionary new architecture has been demonstrated in both software and hardware testing to increase the performance of tensegrity robots and has the potential to be extensible to a wide range of tensegrity configurations.

The flexibility and structural compliance of the biological shoulder joint allows humans to perform a wide range of motions with their arms. The current paper is a preliminary study in which we propose a structurally compliant robotic manipulator joint inspired by the human shoulder joint, which elastically deforms when actuated. The tensile actuation is similar to the contraction and extension of biological muscles. We present four separate models for the shoulder: a simple saddle, a complex saddle, a suspended tubercle, and interlocked tetrahedrons. The analysis explores the dynamics in each design to compare the inherent advantages and disadvantages, which gives insight into the design and development of better interfaces for biologically inspired human-oriented robotics.

In recent years, an increasing number of mobile electronic products such as mobile communicators, combining the functions of a mobile phone and a PDA are beginning to emerge. These devices are highly miniaturized and yet provide a variety of functions at ever higher speeds. Additionally, the product cycle time is getting faster, requiring short design and production cycles at ever lower cost. These trends are posing great set of challenges for the microelectronics and packaging and assembly industry. There seem to be two approaches to solve these challenges-system-in-package (SIP) by stacking of packaged integrated circuits (ICs) or system-on-package (SOP) by stacking of packages with embedded active and passive components. The buried components in SOP require significantly less space in the Z direction, thereby allowing the formation of three-dimensional (3-D) stackable packages. In this paper, two approaches for stacking SOPs were presented, the so-called chip-in-polymer (CIP) technology and duromer molded interconnect device (MID)/WLP technology.

Area array packages (flip chip, CSP (Chip scale packages) and BGA) require the formation of bumps for the board assembly. Since the established bumping methods need expensive equipment and/or are limited by the throughput, minimal pitch and yield, the industry is currently searching for new and lower cost bumping approaches. The experimental work of stencil printing to create solder bumps for flip chip devices is described in detail in this article. In the first part of this article, a low cost wafer bumping process for flip chip applications will be studied in particular. The process is based on an electroless nickel under bump metallization and solder bumping by stencil printing. The experimental results for this technology will be presented, and the limits concerning pitch, stencil design, reproducibility and bump height will be discussed in detail. In the second part, a comparison of measured standard deviations of bump heights as well as the quality demands for ultrafine pitch flip chip assembly are shown.

The encapsulation and packaging reliability in fully integrated, fully wireless 100 channel Utah Slant Electrode Array (USEA)/integrated neural interface-recording version 5 (INI-R5) has been evaluated by monitoring the extended long term in vitro functional stability and recording longevity. The INI encapsulated with 6-μm Parylene-C was immersed in phosphate buffer saline (PBS) at room temperature for a period of over 12 months. The USEA/INI-R5, while being soaked was powered and configured wirelessly through 2.765 MHz inductive link and the transmitted frequency shift keying (FSK) modulated radio-frequency (RF) (900 MHz industrial, scientific, medical-ISM band) signal was also recorded wirelessly as a function of soak time. In order to test the long term recording ability, in vitro wireless recording was performed in agarose for few channels. The full functionality and the ability of the electrodes to record artificial neural signals even after 12 months of PBS soak provides a measure of encapsulation reliability, the functional and recording stability in fully integrated wireless neural interface and potential usefulness for future chronic implants.

Distributed embedded sensor and actuator platforms will be at the core of any research initiatives on smart objects. In this context, recent developments in wireless sensing and micro-sensor technologies provide foundation platforms for considering the development of effective modular systems. They offer the prospect, currently at a prototyping level, of flexibility in use and network scalability. Wireless sensor devices are the hardware building blocks required to construct the core elements of wireless sensor networks. A number of large scale research programmes have developed over the last few years to explore these emerging technologies. We review some of the largest of these, including a review of the current wireless sensor integration technologies. This chapter will also look more closely at some of the more well-known wireless motes that are being used as toolkits for research, development and field trials.

Ambient intelligence (AmI) relies upon the integration of sensors with read-out and signal conditioning circuits, on feed-back mechanisms (e.g. actuators) and not least on the integration of telecommunication components to link these building blocks to a central unit or to a set of distributed computing entities. Sensors represent the ‘eyes’, ‘ears’, ‘nose’ and ‘touch’ equivalents of the human senses and based upon these, a multitude of Ambient Intelligence (AmI) scenarios have been developed [1–3]. Beyond that, sensors provide access to parameters not perceived by humans, enabling additional monitoring, prediction and reaction scenarios [4]. This chapter provides an overview of the sensors and in particular the micro-electromechanical system (MEMS) devices that have developed to provide an AmI sensor interface in the future.

Recent years have shown the tremendous need for visual recording in consumer, telecom and security. Especially mobile phones have driven that trend to today's ultra-small cameras embedded into the handset. While the image capture IC features ever-decreasing pixel geometries and surging megapixel numbers, the readout circuitry and optical systems are now challenged to follow-up with this trend. This paper describes a miniaturization approach using advanced packaging techniques for the electronic system (bare die assembly in stack-wirebond and flip chip) onto a high density circuit board and leveraging a MEMS based optical system providing the possibility for a variable focus lens and aperture concept. This can give rise to a camera including the optical system with just ~3 mm times 10 mm times 10 mm total dimensions. For prototypes, some electronic bare dice are mimicked by de-capsulating the IC from the plastic housing and re- bumping it for use as flip chip. This prototype procedure is also described. Operation of the MEMS device challenges the assembly technique for particulate free manufacturing of all back end processes. Bare die assembly with wirebond and flip chip provides ultimate miniaturization onto a rigid-flex multi layer PCB. The process flow for MOEMS assembly, electronic components assembly and final housing is designed to be generically applicable to current and future needs of ultraminiaturized cameras.

A wireless interconnection scheme based on capacitive coupling provides mono- and bi-directional transmission capabilities for 3-D system integration. Chips are implemented in 0.13 mu m CMOS technology and assembled face-to-face at die-level. RX-TX circuits are specifically designed for low-power functionality and the implementation takes advantage of the two different voltage thresholds that are available for the standard transistors in the CMOS process we used. The communication circuits are coupled via electrodes with an area down to 8 x 8 mu m(2) and this enables the vertical propagation of clock signals at 1.7 GHz, a propagation delay of 420 ps for general purpose signals and a throughput of more than 22 Mb/s/mu m(2) with 0.08 pJ/b energy consumption.

The degree of integration of modern circuits has gone from singledie towards multi-die or even system partition integration. System-In-Package concepts allow to integrate in a hybrid form circuit components steming from different manufacturing processes e.g. CMOS, GaAs, MEMS as well as SMD chips. Combining Flip Chip technology, advanced PCB manufacturing, advanced assembly processes and large area overmolding, highly integrated and reliable sub-systems can be created. The paper describes the individual process steps for a GSM-Power Amplifier module, integrating the PA as a flip chip with the matching SMD components into a novel QFN concept featuring a laser structured bump-on-pad interconnect technology. Large area overmolding covers and protects the entire subsystem thus created. Manufacturing issues as well as specific fabrication details are highlighted and a reliability test shows the performance of the concept under harsh environmental load.

A new packaging technology for a micro-electro-mechanical system (MEMS) pressure sensor was developed to allow the integration of the sensor in a probe mounted on the outside of the airplane. Thus this packaging concept will increase the reliability of equipment by avoiding extra pneumatic connections. Intrinsic advantages of this approach are the avoidance of pressure leaks and the elimination of bad pneumatic connection risk during installation or maintenance phases.

This paper presents a 3-D interconnection scheme based on capacitive coupling. We propose synchronous communication circuits, based on a precharge and transmission approach, that provide an optimization of interconnection sensitivity. Measurements on a 0.13 m CMOS implementation demonstrate working connections with an area occupation of 8 × 8 m2. Experimental results are presented for both die-to-die and wafer-to-wafer assembly techniques. They show a maximum communication bandwidth of 1.23 Gb/s, leading to a throughput per area of 19 Mb/s/m2 with an energy consumption of 0.14 mW/Gb/s. BER measurements demonstrate the reliability of these AC interconnections with no error on more than 1013 bits transmitted.

This paper depicts the concept of micro part manipulation by electrical fields to achieve a high precision, highly parallel batch assembly of components required to put Microsystems together. The concept of orienting microparts in 3D as well as precision alignment on a temporary precision carrier substrate is described and simulations are performed to identify an optimal configuration of the electrical field. In order to move the microparts, they are included in a liquid droplet of high dielectric constant, allowing for fast movement and easy control. The concept implementation idea is briefly described and the required electrode structure is depicted.

Miniaturization is often targeting only individual aspects of a system, e.g. making specific components smaller. A more successful approach is trying to employ synergetic engineering to minimize not only individual components but targets to system as such and uses a top down methodology to minimize the size of a complex product. For the described application, a miniaturized voltage converter, several miniaturization approaches have been merged with 3D assembly technology and flex substrates in order to achieve a target sizeof /spl sim/1cm3. Bare die assembly, an innovative approach to wire the coils utilizing advanced PCB technology, a product specific magnetic ferrite core and area array assembly techniques with reflow encapsulant and finally flex substrates which are folded into the final shape are utilized to realize the product demonstrator. All aspects of the technology were verified against manufacturing capabilities of a medium-sized company, allowing them to fabricate the device for the use in today's mobile products.

The new challenge is to incorporate not only passive components, but as well active circuitry (ICs) and the necessary thermal management. Ultra thin chips (i.e. silicon dies thinned down to

The demand to miniaturize products especially for mobile applications and autonomous systems is continuing to drive the evolution of electronic products and manufacturing methods. To further the miniaturization of future products the integration of functions on miniaturized subsystems, i.e. System-in-Package (SiP) is a promising approach. Here, use of recent manufacturing methods allows to merge the SiP concept with a volumetric integration of IC’s. Up to now, most of the systems make use of single- or double-sided populated system carriers. A new challenge is to incorporate not only passive components, but as well active circuitry (IC’s) and the necessary thermal management. Ultra thin chips (i.e. silicon dies thinned down to

MEMS devices may exhibit delicate structures sensitive to damage during handling or environmental influences. Their functionality may furthermore depend on sealing out the ambient or being in direct contact. Stress, thermal load or contaminations may change their characteristics. Here packaging technology is challenged to extend from microelectronics towards MEMS and MOEMS. Today's approaches typically rely on housing the miniature devices in bulky ceramic or metal casing or putting them into very high volume production-, benefiting from the microelectronics packaging infrastructure. Alternatively, besides focusing on available technology, device manufacturers develop individual packages for their product typically at high cost. While there is nowadays a good infrastructure for MEMS realization from universities to MEMS foundries, packaging still remains as a bottleneck at the end of the design cycle, sometimes stopping a device from being commercialized. Selecting the proper packaging method may tip the scale towards a product success and a product failure. Choosing the right technology therefore is not only a marginal work package but also a crucial part of the product design. Three approaches to be applied for MEMS/MOEMS devices will be presented and highlighted by examples. Single die packaging, die-to-wafer processes as well as wafer level packaging options are detailed with their individual benefits and challenges. Mechanical, fluidic and optical aspects are reflected in the package technologies selected for the individual examples presented. Accelerated testing of the packaged devices under actual conditions may also be a stumbling block; one example on an optical microsystem will showcase this issue, highlighting system response under different environmental loads.

As the number of applications for flexible assemblies is growing there is also a larger variation of requirements for such packages. Therefore different technologies have been developed for applications from CSP's to smart cards. The scope of the paper is to describe different approaches for packaging using ultra-thin and flexible chips. This includes the assembly processes as well as packaging concepts e.g. CSP's, 3D modules and volumetric integration of passive and active components into modules and substrates.

MEMS packaging plays an important role within the function of the MEMS device. Besides the electrical interconnection, the package provides mechanical protection. It must enable the resulting package to be manufactured and assembled at low cost. Also, high reliability requirements even under harsh conditions must be fulfilled in order to be accepted in the market. Capping and hermetic sealing of MEMS devices is a key factor in enabling them to be processed with further packaging steps. Instead of developing for each device an adapted packaging process, there is a requirement to provide a technology platform that enables a fast, low cost processing of protected devices. Wirebonding can be used to overcome the 3D wiring issues and provide a fast and mature process with a well established infrastructure to realize packaged MEMS devices with minimal dimensions. Solder balls terminate the electrical interconnects, allowing a seamless integration into a SMD compatible process. This paper presents the concept, the technical realization of this approach and the extension to a full wafer level chip scale MEMS package.

Merging intelligence with power is one of the hot topics of the last few years. Not only driven by the automotive industry, but also by industrial electronics and consumer electronics, large markets await solutions to joint low power microcontrollers with high power semiconductor switches or regulators. Until now, standard surface mount technology has dominated, although hybrid assemblies also have their market niches. Miniaturisation by integrating the required semiconductor in the form of bare dice into a single package is still a challenge. Chip on board provides a technically feasible solution, but COB has only limited compatibility to the process used for passive component mounting in this package. Flip chip would provide the ultimate solution here, allowing fully SMD compatible processing. Unfortunately, power devices must pass tens of amperes through the contacts and must also dissipate a high thermal load. A detailed investigation to verify reliability under these conditions must be conducted. This paper evaluates the performance of flip chip contacts under both thermal and electrical load. Thermal simulation and metallurgical investigations show the performance of flip chip technology for power assemblies.