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Runtime noise management systems typically rely on on-chip noise sensors to accurately capture voltage emergencies. As such, the threshold voltage for noise sensors to report emergencies serves as a critical tuning knob between the system failure rate and false alarms. Unfortunately, the problem of optimal threshold voltage computation remains open in literature despite its importance. The problem is further complicated by process variations, which introduce significant variations in load currents and thus in noise across different chips. A uniform noise margin may not work optimally for all the chips. In this paper, we first formulate the problem of minimizing the system alarm rate subject to a given system failure rate constraint. We then put forward a uniform scheme to find an optimal solution for all chips. Compared to a seemingly more intuitive approach which is too conservative, experimental results over a set of industrial designs show an average of 20.6% reduction in system alarm rate under the same system failure rate constraint. We further show that with the help of ${I} _{\mathrm {ddq}}$ measurements during testing which reveal process variation information, it is possible and efficient to compute a per-chip optimal threshold voltage threshold. It further reduces the alarm rate by 12.3% on average compared with uniform threshold approach. To the best of the authors knowledge, this is the first in-depth study on optimal threshold voltage computation for noise sensors. We hope that it shall point out new directions for systematic studies of on-chip noise sensor utilization.

A sub-threshold design could provide a compelling approach to power critical applications. An exponential relationship exists, however, between the delay and the threshold voltage, that makes this design-time timing closure extremely difficult, if not impossible, to achieve. Several previous studies were focused on the technique of body biasing during post-silicon tuning for delay compensation. But they were mostly for super-threshold designs where spatially correlated ${L} _{\mathbf {eff}}$ variation dominates. They cannot be applied directly to sub-threshold designs in which purely random threshold voltage variations dominate. These works also assumed multiple body biasing voltage domains and multiple body biasing voltage levels, which involve significant design overhead. The problem of selective body biasing for post-silicon tuning of sub-threshold designs is examined in this paper. The possibility of using only one body bias voltage domain with a single body bias voltage is explored. The problem was formulated first as a linearly constrained statistical optimization model. The adaptive filtering concept from the signal processing community was then adopted so that an efficient, yet novel, solution could be developed. Using several 65 nm industrial designs, experimental results suggest that, compared with a seemingly more intuitive approach, the proposed approach can improve the pass rate by 57% on average with similar standby power and the same number of body biasing gates. This approach can reduce the standby power, on average, by 84%, with a 20% pass rate loss, more than the approach to bias all the gates.

DRAM renovation calls for a holistic architecture exploration to cope with bandwidth growth and latency reduction need. In this paper, we present DRAM area power timing (DArT), a DRAM area, power, and timing modeling tool, for array assembly and interface customization. Through proper design abstraction, our component-based modeling approach provides increased flexibility and higher accuracy, making DArT suitable for DRAM architecture exploration and performance estimation. We validate the accuracy of DArT with respect to the physical layout and circuit simulation of an industrial 68 nm commodity DRAM device as a reference. The experiment results show that the maximum deviations from the reference design, in terms of area, timing, and power, are 3.2%, 4.92%, and 1.73%, respectively. For an architectural projection by porting it to a 45 nm process, the maximum deviations are 3.4%, 3.42%, and 8.57%, respectively. The combination of modeling performance, flexibility, and accuracy of DArT allows us to easily explore new DRAM architectures in the future, including 3-D stacked DRAM.

Presented is a novel half Gb DRAM device for 3D stacked systems utilizing TSV. It is designed through the use of a new computer-aided design methodology and which realizes 819 Gb/s bandwidth across 16 channels and

Three-dimensional integrated circuits (3D ICs) have drawn groundswell of interest in both academia and industry in recent years. However, the power integrity of 3D ICs is threatened by the increased current density brought by vertical integration. To enhance reliability, the locations of power/ground through-silicon-vias (P/G TSVs), which are used to deliver power/ground signals to different layers, must be carefully placed to minimize IR-drop. However, the currents in 3D ICs are not deterministic and exhibit both spatial and temporal correlations. In view of this, we propose a correlation based heuristic algorithm for P/G TSV placement. Unlike most existing works, the proposed algorithm does not need iterations of full-grid simulations. Thus, it is especially attractive for large designs with millions of nodes. Experimental results on TSMC 90nm industrial designs indicate that the proposed method can achieve up to 70% reduction in IR-drop compared with the current industry practice, which uniformly distributes P/G TSVs.

Power supply noise has become one of the primary concerns in low power designs. To ensure power integrity, designers need to make sure that voltage droop and bounce do not exceed noise margin in all possible scenarios. Since it is very difficult to capture the exact worst corner among the mist of complex functionalities in modern VLSI designs, statistical design methodologies have been adapted, which may bring significant design overhead. In view of this, various runtime techniques have been proposed in literature to suppress power grid noise adaptively. This paper first presents various challenges in power grid designs from an industrial perspective, explains the difficulties in handling them at deign time, and then reviews various runtime techniques to adaptively suppress power supply noise, including sensor-based power gating, re-routable decaps, proactive clock frequency actuator, and PLL based clocking.

Paralleling square unit capacitors have been commonly used for Switched-Capacitor circuits to achieve higher accurate capacitor ratio. However, the capacitor ratio may be shifted due to the wire interconnection of these unit capacitors. The small capacitor ratio shift may cause a significant yield drop. The ratio shift can be reduced by using extra circuitry to achieve parasitic insensitive design. This study presents a simple a layout modification to alleviate the ratio shift, thus enhancing yield, without requiring extra circuitry.

The biggest contributors to the substrate noise are supply noises, since the power and ground wires are directly connected to the silicon substrate for CMOS digital cells. Clock trees in large digital designs can acquire large power consumption when thousands of flip-flops transitioning through the switching zone. Memories also draw significant instantaneous power when being accessed. In this paper, a measurement of the substrate noise in conjunction with the supply noises analyses were conducted on a real circuit system. The measured substrate noise waveforms were proportional to the power consumptions and substantially correlated with the supply noises for each test condition. As a result, these observations could be useful for modeling substrate noise effects and developing prevention methods.