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This Special Section of the IEEE Journal of Solid-State Circuits (JSSC) features expanded versions of papers selected from those presented at the 48th ESSCIRC Conference, held at Technische Universitat Dresden, Dresden, Germany, during September 3–6, 2018.

Dear Readers, The editorial board is pleased to welcome you to the IEEE Open Journal of the Solid-State Circuits Society (OJ-SSCS). Our first papers will soon be available online via the IEEEXplore® platform.

This paper describes a 4.3B transistors, 15-cores, 30-threads enterprise Xeon® processor with a 37.5 MB shared L3 cache implemented in a 22 nm 9M Hi-K metal gate tri-gate process. A modular floorplan methodology enables easy chops to 10 and 6 cores. Multiple clock and voltage domains are used to reduce power consumption. The clock distribution uses a single PLL per column to save power and minimize deskew crossing points. Integrated PCIe Gen3 and Quick Path Interconnect® (QPI) ports operate at 8GT/s. The 4-channel memory interface supports both 1866 MT/s DDR3 and a new memory buffer interface running at 2667 MT/s on the same pins. The core, cache and I/O recovery techniques improve manufacturing yields and enable multiple product flavors from the same silicon die.

There are few papers which aim to analyze the effects of laser marking for traceability on various materials; therefore, the present paper proposes a study of the influences of such radiation processing on a titanium alloy, a vastly used material base within several industry fields. For the novelty impact, femtolaser marking has been carried out, besides the commercial nanosecond standard engraving. All marks have been analyzed using scanning electron microscopy, energy dispersive X-ray spectroscopy and X-ray diffractometry.

This paper describes a 2.3 Billion transistors, 8-core, 16-thread, 64-bit Xeon® EX processor with a 24 MB shared L3 cache implemented in a 45 nm nine-metal process. Multiple clock and voltage domains are used to reduce power consumption. Long channel devices and cache sleep mode are used to minimize leakage. Core and cache recovery improve manufacturing yields and enable multiple product flavors from the same silicon die. The disabled blocks are both clock and power gated to minimize their power consumption. Idle power is reduced by shutting off the unterminated I/O links and shedding phases in the voltage regulator to improve the power conversion efficiency.

This issue includes a total of 16 analog/RF papers and four digital papers. The papers are briefly introduced here.

The next-generation enterprise Xeon® server processor has 15 dual-threaded 64b Ivybridge cores [1] and 37.5MB shared L3 cache. The system interface includes two on-chip memory controllers, each with two memory channels and supports multiple system topologies. The processor has 4.31B transistors in a high-κ metal-gate tri-gate 22nm CMOS technology with 9 metal layers [2]. The design supports a wide array of product offerings with thermal design power ranging from 40 to 150W and frequencies ranging from 1.4 to 3.8GHz. Fig. 5.4.1(a) shows the processor block diagram. The floorplan (Fig. 5.4.1(b)) is driven by the ring bus routability and latency, as well as the chop requirements to smaller core counts. The cores and associated L3 cache are organized in columns of five, with the ring bus segment embedded. The fully populated die has 15-cores in three columns. The 10-core chop removes the rightmost 3rd column and its dedicated top and bottom IOs. CMOS muxes embedded in the ring bus are programmably operable in a 2-or-3-columns configuration. The 6-core chop removes the 2nd and 4th rows from the 10-core die.

The 13 papers in this special issue are extended versions of papers presented at the 35th European Solid-State Circuits Conference (ESSCIRC), held September 14-18, 2009, in Athens, Greece. There are a total of six RF papers, five analog papers and two digital papers.

This 45nm 1.1V unidirectional differential point-to-point link interface achieves 6.4GT/s transfer rate. To support 17 inches, 2-connector channel topology required by MultiProcessor (MP) platform, it utilizes two novel current compensation techniques that optimize the performance/power ratio of the transmitter output swing level and receiver gain/bandwidth.

A 2.3B transistors, 8-core, 16-thread 64-bit Xeon® EX processor with a 24MB shared L3 cache was implemented in a 45nm 9-metal process. Multiple clock and voltage domains are employed to reduce power consumption. Long channel devices and cache sleep mode are used to minimize leakage. Core and cache recovery improve manufacturing yields and enable multiple product flavors using the same silicon die and package. The disabled blocks are both clock and power gated to minimize their power consumption. Idle power is reduced by shutting off the un-terminated I/O links and shedding phases in the voltage regulator to improve the power conversion efficiency.

This paper presents the power reduction and management techniques for the 45nm, 8-core Nehalem-EX processor. Multiple clock and voltage domains are used to reduce power consumption. Long channel devices and cache sleep mode are used to minimize leakage. Core and cache recovery improve manufacturing yields and enable multiple product flavors from the same silicon die. Clock and power gating minimize power consumed by disabled blocks. An on-die microcontroller manages voltage and frequency operating points, as well as power and thermal events. Idle power is reduced by shutting off the un-terminated I/O links and shedding phases in the voltage regulator to improve the power conversion efficiency.

Multiple clock and power domains are widely used to manage power in modern nanoscale designs. This Forum will present the latest design techniques in multiple-domain clock and power management for high-performance processors, as well as low-power systems-on-chip (SoC). Topics include clock and data synchronization, power gating, floorplan and layout implications, clock and power grids, test requirements, modular design techniques. Practical examples will be presented from both industry and academia.

A 65 nm 1.2 V GTL bus interface achieves 800 MT/s 6.4 GB/S data rate in a 3-load multi-processor (MP) environment. To enable a 20% increase in data rate compared to previous design, it utilizes a staged driver, DLL controlled predriver, Tco compensation, data/strobe time shifter, high gain differential amplifier as well as advanced process, voltage and temperature (PVT) compensation design.

A 130nm 1.2V GTL bus interface with compensated slew rate and termination achieves 667MT/S 10.7GB/S data rate in a 3-load MP environment. The design utilizes preboost and postboost methods, current steering circuit to minimize simultaneous switching noise and negative hysteresis to speed up the common-clock delay. The design also incorporates system-level I/O loopback for system timing marginality test