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Dynamic voltage scaling (DVS) is an effective strategy in reducing the power consumption of a processor through adjusting its supply voltage at runtime. The power converter that drives the processor should have a wide output voltage range and fast reference-tracking response while maintaining a high efficiency. For such applications, inductive switching converters are suitable candidates [1-4]. To enhance the transient response and to reduce the size of off-chip components, DC-DC converters switching in the 10MHz range are studied recently. When switching at a high frequency, efficiency is compromised as the switching loss becomes significant. Moreover, comparator delay of a few ns causes serious over-charging and over-discharging of the ramp capacitor and the delay also limits the maximum duty cycle of the converter. A current-mode control needs an on-chip current sensor that would consume too much power when running in the 10MHz range. In [5], a 5MHz converter employs auto-selectable peak- and valley-current control, but the duty cycle range is limited to 0.6. A higher switching frequency (fs) would further reduce this range and would not be applicable for DVS. Therefore, a voltage-mode control with Type-III compensation for loop bandwidth extension becomes an attractive solution. However, a conventional Type-III compensator needs large on-chip compensation capacitors and resistors. In [6], a pseudo Type-III compensator reduces the value and thus size of those components, however, it requires adding lowpass and bandpass functions that complicates the design, and furthermore it does not use any special technique for fast reference tracking.

In this paper, a 10/30MHz PWM buck converter with an accuracy-improved ramp generator is proposed. To extend the minimum duty ratio of the converter, the valley of the ramp signal is controlled to be larger than 0.2V by the threshold voltage of an NMOS transistor. To shorten the delay time of the comparator in the ramp generator, a high speed two-stage push-pull comparator is presented. Simulation results of the ramp generator with switching frequencies from 10MHz to 30MHz show that the error due to process variations for the ramp, clock and maximum duty ratio are not larger than 10%. To avoid the design of high speed current sensor and maximize the unity-gain frequency of the regulation loop, voltage mode control with type III compensation is adopted for the converter. Measurement results show that the proposed buck converter with 500mA of load range has good steady-state and transient performances for 10MHz and 30MHz of switching frequencies, respectively.

Continuous-time common-mode feedback (CMFB) detector circuits for a fully differential amplifier with improved common-mode voltage detection accuracy are proposed, designed and analyzed. Firstly, we analyzed the proposed N-type CMFB detector, showing that it has two turning points when the differential voltage increases and it achieves very small deviation from the detected common-mode voltage. By combining the N-type and the P-type components directly, the proposed complementary CMFB detector circuit has further improved detection accuracy, and the simulation results with 0.13µm IBM process show only 6mV variation for rail-to-rail differential input voltage. A fully differential high gain wide bandwidth amplifier with the proposed CMFB detector circuit is designed and the simulation results have verified the proposed CMFB detector circuits.

A chip-area-efficient CMOS low-dropout regulator (LDR) based on a wide-swing voltage buffer is proposed for battery-powered portable applications. By using a low-threshold PMOS with a novel parabolic adaptive biasing technique in the buffer, the voltage overhead is dramatically reduced, allowing a small-sized power transistor that works in the linear region at heavy load to be used while still maintaining a large load range and a tight regulation. The operation principle and the stability issues of using low-ESR output capacitor without any compensation capacitors are discussed. The proposed LDR has been fabricated in a standard 0.13-μm CMOS process, and highvoltage devices are used for the power transistor and in the error amplifier to accommodate for the Li-Ion battery voltage range. With 0.2V dropout voltage and 200 mA maximum load current, the measured load regulation is 85 μV/mA while the occupied active chip area is only 0.045mm2.

This paper presents a fast-transient-response hybrid buck converter (HBC) which consists of a voltage mode PWM switching converter with Type III compensation and two auxiliary linear regulators for portable applications. With techniques of hysteretic load transient detection and adaptive duty ratio compensation, the proposed HBC achieves automatic and nearly-seamless loop transition during load transient to achieve small voltage dip and short recovery time. The auxiliary linear regulators can be automatically deactivated in the steady state such that the power efficiency of the switching converter is not compromised. Experimental results of a 0.13-μm CMOS prototype with 10 MHz switching frequency show that, compared with the conventional design, the proposed HBC reduces the voltage dip from 145mV to 55mV and the recovery time from 7.0μs to 1.5μs for a 300mA load current step-up within 20ns.

A novel super-bandwidth three-stage amplifier with a new stability method are proposed in this paper. It could produce two left-half-plane zeros to compensate the two non-dominant poles and the dominant pole, which makes the amplifier had very large bandwidth and good phase margin. Moreover, only one Miller capacitor is required, and consumes not large power consumption when driving a large load capacitor. The simulation results show that for 1.5V power supply, a GBW of 22MHz, DC gain of 100 dB, PM of 62° and power dissipation of 0.708mW can be achieved for a load capacitor of 120pF and 2pF Miller compensation capacitor in 0.5?m CMOS technology. Finally, corner analysis shows that the proposed amplifier is suitable for engineering applications.