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Grain boundaries between 60° rotated and twinned crystals constitute the dominant type of extended line defects in two-dimensional transition metal dichalcogenides (2D MX2) when grown on a single c...

Electron channeling contrast imaging (ECCI) is a powerful technique to characterize the structural defects present in a sample and to obtain relevant statistics about their density. Using ECCI, such defects can only be properly visualized, if the information depth is larger than the depth at which defects reside. Furthermore, a systematic correlation of the features observed by ECCI with the defect nature, confirmed by a complementary technique, is required for defect analysis. Therefore, we present in this paper a site-specific ECCI-scanning transmission electron microscopy (STEM) inspection. Its value is illustrated by the application to a partially relaxed epitaxial Si0.7Ge0.3 on a Si substrate. All experiments including the acquisition of ECCI micrographs, the carbon marking and STEM specimen preparation by focused ion beam, and the in-situ-subsequent-STEM-in-scanning electron microscopy (SEM) characterization were executed in one SEM/FIB-based system, thus significantly improving the analysis efficiency. The ECCI information depth in Si0.7Ge0.3 has been determined through measuring stacking fault widths using different beam energies. ECCI is further utilized to localize the defects for STEM sample preparation and in-situ-subsequent-STEM-in-SEM investigation. This method provides a correlative 2.5D defect analysis from both the surface and cross-section. Using these techniques, the nature of different line-featured defects in epilayers can be classified, as illustrated by our study on Si0.7Ge0.3, which helps to better understand the formation of those detrimental defects.

The epitaxial growth of Si layers on Si substrates in the presence of O atoms is generally considered a challenge, as O atoms degrade the epitaxial quality by generating defects. Here, we investigate the growth mechanisms for Si epitaxy on O atomic layers (ALs) with different O-contents and structures. O ALs are deposited by ozone (O3) or oxygen (O2) exposure on H-terminated Si at 50 °C and 300 °C respectively. Epitaxial Si is deposited by chemical vapor deposition using silane (SiH4) at 500 °C. After O3 exposure, the O atoms are uniformly distributed in Si-Si dimer/back bonds. This O layer still allows epitaxial seeding of Si. The epitaxial quality is enhanced by lowering the surface distortions due to O atoms and by decreasing the arrival rate of SiH4 reactants, allowing more time for surface diffusion. After O2 exposure, the O atoms are present in the form of SiOx clusters. Regions of hydrogen-terminated Si remain present between the SiOx clusters. The epitaxial seeding of Si in these structures is realized on H-Si regions, and an epitaxial layer grows by a lateral overgrowth mechanism. A breakdown in the epitaxial ordering occurs at a critical Si thickness, presumably by accumulation of surface roughness.

In this study, an annular multi-segment backscattered electron (BSE) detector is used in back scatter geometry to investigate the influence of the angular distribution of BSE on the crystalline defect contrast in electron channeling contrast imaging (ECCI). The study is carried out on GaAs and Ge layers epitaxially grown on top of silicon (Si) substrates, respectively. The influence of the BSE detection angle and landing energy are studied to identify the optimal ECCI conditions. It is demonstrated that the angular selection of BSEs exhibits strong effects on defect contrast formation with variation of beam energies. In our study, maximum defect contrast can be obtained at BSE detection angles 53–65° for the investigated energies 5, 10 and 20 keV. In addition, it is found that higher beam energy is favorable to reveal defects with stronger contrast whereas lower energy ( ≤ 5 keV) is favorable for revealing crystalline defects as well as with topographic features on the surface. Our study provides optimal ECCI conditions, and therefore enables a precise and fast detection of threading dislocations in lowly defective materials and nanoscale 3D semiconductor structures where signal to noise ratio is especially important. A comparison of ECCI with BSE and secondary electron imaging further demonstrates the strength of ECCI in term of simultaneous detection of defects and morphology features such as terraces with atomic step heights.

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In this work, we discuss the characteristics of particular island-type features with an amorphous core that are developed during the low temperature epitaxial growth of Ge and GeSn layers by means of chemical vapor deposition with Ge2H6. Although further investigations are needed to unambiguously identify the origin of these features, we suggest that they are originated by the formation of clusters of H and/or contaminants atoms during growth. These would initially cause the formation of pits with crystalline rough facets over them, resulting in ring-shaped islands. Then, when an excess surface energy is overcome, an amorphous phase would nucleate inside the pits and fill them. Reducing the pressure and/or increasing the growth temperature can be effective ways to prevent the formation of these features, likely due to a reduction of the surface passivation from H and/or contaminant atoms.

The ongoing study of {111} planar defects (PDs) in III–V nanowires (NWs) entails a fast and quantitative characterization method beyond transmission electron microscopy (TEM). We report here a simple and reliable method to calculate the PD frequency in InAs NWs using a lab X-ray diffractometer. The fact that the PD distribution is location independent and irrelevant to the NWs diameter in catalyst-free InAs NWs epitaxy makes PD frequency global calculation possible. We demonstrated that the PDs follow a geometric distribution in NWs. As a consequence, applying a 1D disordered layers diffraction model, we relate the diffraction peak angle directly to the PD frequency. The calculated PD frequency values are in good agreement with that extracted from high resolution TEM analysis. As an example, we applied this method to study the influence of growth temperature on PD frequencies in the frame of a 2D nucleation model.

Epitaxial Si-O superlattices consist of alternating periods of crystalline Si layers and atomic layers of oxygen (O) with interesting electronic and optical properties. To understand the fundamentals of Si epitaxy on O atomic layers, we investigate the O surface species that can allow epitaxial Si chemical vapor deposition using silane. The surface reaction of ozone on H-terminated Si(100) is used for the O deposition. The oxygen content is controlled precisely at and near the atomic layer level and has a critical impact on the subsequent Si deposition. There exists only a small window of O-contents, i.e. 0.7–0.9 atomic layers, for which the epitaxial deposition of Si can be realized. At these low O-contents, the O atoms are incorporated in the Si-Si dimers or back bonds (-OSiH), with the surface Si atoms mainly in the 1+ oxidation state, as indicated by infrared spectroscopy. This surface enables epitaxial seeding of Si. For O-contents higher than one atomic layer, the additional O atoms are incorporated in the Si-Si back bonds as well as in the Si-H bonds, where hydroxyl groups (-Si-OH) are created. In this case, the Si deposition thereon becomes completely amorphous.

Ge has been considered as a promising candidate for the active region in optical interconnect applications such as lasers and photodetectors, since its band gap corresponds to a wavelength with less loss in SiO2 waveguides. However, to increase the efficiency of these applications, a direct band gap material is required. Incorporation of Sn into Ge has been considered to obtain a direct band gap material [1,2]. According to theoretical calculations [3], the critical Sn content to achieve the direct transition depends on the strain. When the GeSn layer is fully relaxed, around 11% of Sn is required. On the other hand, when the layer experiences compressive strain, the critical Sn content increases. One option to obtain highly strain-relaxed GeSn with high Sn content is to increase the thickness of the GeSn layer. In addition, the active region of the optical devices has to be thick to obtain a high efficiency. However, it is well known that Sn segregation to the surface easily occurs [4], which results in Sn precipitation/agglomeration on the surface when a thick layer is grown. The Sn agglomeration is the result of the collision among Sn atoms on the surface. Therefore, we focused on the freezing of Sn atoms during GeSn growth. GeSn layers were grown with Ge2H6 and SnCl4 precursors on Ge(001) substrates at 320°C by atmospheric CVD in an Epsilon like equipment from ASM. The target thickness of the GeSn layers is 200 nm. N2 and H2 with different flows ranging from 10 to 40 slm were used as carrier gases to study the impact of the partial pressure of the precursors on Sn agglomeration. It is expected that using low carrier gas flows enhances the Sn freezing due to the higher Ge2H6 and SnCl4 partial pressures. In addition, it is expected that switching the carrier gas from N2 to H2suppresses the Sn migration on the surface due to the resulting surface H-termination. We found opposite tendencies for the surface Sn agglomeration as a function of the H2 and N2 carrier gas flow. A lower N2 suppresses the surface Sn agglomeration. As we expected, a high partial pressure of the precursors enhances the freezing of Sn atoms into the subsurface. On the other hand, when H2 is used as a carrier gas, a higher H2 flow suppresses the surface Sn agglomeration. The growth temperature (320°C) is close to the temperature at which adsorbed H starts to desorb thermally from the Ge surface (340°C) [5, 6]. However, a high H2 partial pressure may suppress the desorption of surface H which is provided by the deposition by Ge2H6. The Sn segregation should be suppressed by the surfactant effect of surface H [6]. The different behavior of these two carrier gases will be discussed in detail. [1] D. W. Jenkins and J. D. Dow, Phys. Rev. B, 36, 7994 (1987). [2] M. R. Bauer, et al., Solid State Commun. 127, 355 (2003). [3] Y. Shimura, et al., J. Appl. Phys. submitted. [4] E. Kasper, et al., Thin Solid Films, 520, 3195 (2012). [5] L. Surnev and M. Tikhov, Surf. Sci. 138, 40 (1984). [6] A. Sakai and T. Tatsumi, Appl. Phys. Lett. 64, 52 (1994).

Band engineered Si/O superlattices are promising channel materials for ultimately scaled complementary metal oxide semiconductor devices. Theoretical calculations have indicated that insertion of O monolayers into Si lattice creates anisotropy in the Si band structure with an enhanced carrier mobility in the channel direction. However, the experimental demonstration of such superlattices is not straightforward, as it requires processes for the deposition of a monolayer of O on Si, and to continue the Si epitaxy thereon. In this work, we investigate processes for the fabrication of Si/O superlattices using the chemical vapor deposition technique. Ozone is used for the O deposition with control of the deposited O content at the monolayer level. The SiH 4 based Si deposition is performed at low temperatures (500 °C–550 °C) in order to obtain a confined O monolayer in the Si superlattice. Si deposited on O layer of 1.2 O monolayers is completely amorphous. This indicates that this O layer is extremely uniform as it prevents any epitaxial ordering with the substrate. Reducing the O content to 0.9 O monolayers in combination with a slower Si deposition favors epitaxial ordering of Si on O/Si. Finally a defect free Si epitaxy is demonstrated on the O monolayer. Such ordering of epitaxial Si on the O layer provides a promising outlook for the growth of superlattices.

Si cap passivation on Ge shows low border trap response.The Si cap passivation is also suitable for Ge nMOS applications.Low Dit at Ec can be achieved by tuning the amount of Si at the interface.A dry O3 process can be used to control the amount of Si that is oxidized. One route to passivate the Ge/high-? interface is by depositing an epitaxial Si layer on the Ge surface. Subsequently, the Si layer is partially oxidized and a high-? layer is deposited on top. This passivation scheme has proven its efficiency over the last decade for pMOS applications. However, in this paper we demonstrate that this route can also be used for nMOS applications depending on the amount of Si left after the oxidation process. Moreover, the amount of border traps extracted from low frequency capacitance-voltage measurements is low, in contrast to what has been reported on GeO2 passivation. GeO2 passivation results in very low Dit levels at the conduction band edge. Therefore, GeO2 has been put forward as a good candidate for nMOS but it suffers from border traps in the oxide. Si cap passivation can solve both problems: Dit at the interface as well as the border traps in the oxide.

We report two approaches to integrate high quality III-V templates with low defectivity on Si wafers by epitaxial growth. The first approach is based on blanket, InGaAs-based Strain Relaxed Buffers grown by MOVPE on 200mm Si, and the second on the selective area MOVPE of InP in Shallow Trench Isolation structures patterned on 300mm Si. Both structures are characterized structurally and show the efficient trapping and annihilation of defects propagating from the Si/III-V interface. We believe these two approaches represent viable alternatives towards the realization of CMOS-compatible III-V templates and stacks for high-performance devices monolithically integrated on Si.

The concept of atomically controlled processing for group IV semiconductors is based on atomic-order surface reaction control. This approach is especially important for the epitaxial deposition of very thin (nm) layers. Here, the existences of Ge oxide in the CVD reactor resulting from former Ge deposition and hydrogen termination of the wafer surface is impacting the epitaxial growth essentially. Therefore the evaporation of Ge oxide is suppressed by Si coating the reactor before wafer loading and/or Si capping after Ge growth and/or very low temperature SiH4 treatment after wafer loading. By the use of Si0.5Ge0.5 buffer layer, hydrogen termination of the surface is reduced. As a result, nm-order thick Ge epitaxial growth with very short incubation period and the suppression of surface roughness generation is realized.

Electrically active defects in silicon-based epitaxial layers on silicon substrates have been studied by Deep-Level Transient Spectroscopy (DLTS). Several aspects have been investigated, like, the impact of the pre-epi cleaning conditions and the effect of a post-deposition anneal on the deep-level properties. It is shown that the pre-cleaning thermal budget has a strong influence on the defects at the substrate/epi layer interface. At the same time, a post-deposition Forming Gas Anneal can passivate to a large extent the active defect states. Finally, it is shown that application of a post-deposition anneal increases the out-diffusion of carbon from a Si:C stressor layer into the p-type CZ substrate.

Integrating high electron mobility III–V materials on an existing Si based CMOS processing platform is considered as a main stepping stone to increase the CMOS performance and continue the scaling trend. Owing to the polar nature of III–V materials versus the nonpolar nature of Si, antiphase boundaries (APBs) arise in epitaxially grown III–V materials on Si. Here, we demonstrate an approach to restrict the generation of APBs by selectively depositing a III–V material in narrow Si-trenches as formed within the shallow trench isolation (STI) patterned Si(001) wafers. Based on the detailed crystal structures of Si and III–V materials, a concept has been developed comprising the deposition in “v-grooves” with {111} facets in the Si wafer. The grooves are formed by anisotropic wet etching of Si. When InP is deposited selectively into these “v-grooves”, the crystallographic alignment between the Si and InP restricts the APBs nucleation to the corners of the “v-grooved” trench. This approach offers a promising m...

We have investigated the Ga and Sn content dependence of the crystallinity and electrical properties of Ga-doped Ge1-xSnx layers that are heteroepitaxially grown on Ge(001) substrates. The doping of Ga to levels as high as the solubility limit of Ga at the growth temperature leads to the introduction of dislocations, due to the increase in the strain of the Ge1-xSnx layers. We achieved the growth of a fully strained Ge0.922Sn0.078 layer on Ge with a Ga concentration of 5.5 × 1019 /cm3 without any dislocations and stacking faults. The resistivity of the Ga-doped Ge1-xSnx layer decreased as the Sn content was increased. This decrease was due to an increase in the carrier concentration, with an increase in the activation level of Ga atoms in the Ge1-xSnx epitaxial layers being induced by the introduction of Sn. As a result, we found that the resistivity for the Ge0.950Sn0.050 layer annealed at 600°C for 1 min is 3.6 times less than that of the Ga-doped Ge/Ge sample.

In this work, digermane (Ge 2 H 6 ) is investigated as low temperature Ge precursor for Chemical Vapor Deposition. High quality Ge epitaxial growth on Si substrates is reported at temperatures as low as 275 °C and a specific Ge 2 H 6 surface reaction is proposed to explain the growth mechanism at those very low temperatures. In addition, we highlight that Ge 2 H 6 provides solutions, not covered by conventional GeH 4 , for various original Ge-based materials: direct deposition of amorphous Ge layers directly on dielectric or metallic surfaces, as well as the epitaxial growth of smooth, fully strained, monocrystalline GeSn layers on Ge substrates.

CMOS scaling for sub-12 nm nodes will need high-mobility channel semiconductors such as III-V materials to be integrated on large diameter Si substrates. A way to overcome lattice mismatch is to confine defects resulting from strain relaxation on the sidewalls of trenches made by etch-back of Si in standard Shallow-Trench-Isolation (STI) structures. The surface of the InP layers, grown as buffer material in these trenches by selective epitaxy, is planarized by means of CMP, after which it needs to be recessed to allow for the deposition of the III-V channel stack. We have developed an in-situ HCl etching process allowing a close control of the recess depth down to a few nm and leaving a clean and planar InP surface well suited for subsequent III-V epitaxial growth. The process development was carried out in a commercial Aixtron Crius MOCVD reactor on standard SiO2 STI patterned 200 mm Si (001) wafers.

We have demonstrated the formation of Ni(Ge 1− y Sn y ) layers on Ge 1− x Sn x layers by using solid-phase reaction for samples with Sn contents ranging from 2.0% to 6.5%. We have also investigated solid-phase reaction products in Ni/Ge 1− x Sn x /Ge samples after annealing and the crystalline properties of nickel–tin–germanide layer/Ge 1− x Sn x contact structures. After annealing at temperatures ranging from 350 to 550 °C, the formation of polycrystalline Ni(Ge 1− y Sn y ) layers has been observed on epitaxial Ge 1− x Sn x layers with Sn contents ranging from 2.0% to 6.5%. We also observed anisotropic crystal deformation of NiGe with the incorporation of Sn atoms into substitutional sites in NiGe. In the case of the Ni/Ge 1− x Sn x /Ge sample with a Sn content of 3.6%, the formation of an epitaxial Ni 2 (Ge 1− z Sn z ) layer on the Ge 1− x Sn x layer was found. The formation of β-Sn crystallites was observed after annealing at above 450 °C in samples with a high Sn content of 6.5%. This β-Sn formation is due to the precipitation of Sn atoms. In all samples annealed at 350 °C, the morphology of Ni–Ge–Sn layers is smooth and uniform. However, the surface roughness and interface roughness increase for an annealing temperature of 550 °C. In particular, in the sample with a Sn content of 6.5%, the temperature at which agglomeration noticeably occurs is as low as 450 °C.

In this paper, we propose the fabrication of whole strained Ge complementary metal–oxide-semiconductor (CMOS) with Ge 1− x Sn x materials as stressors to outperform the state-of-the-art uniaxial compressive strained Si CMOS. Ge 1− x Sn x materials have larger lattice constant than that of Ge, which can apply the strain into Ge channel region. Firstly, we have demonstrated p-type doped Ge 1− x Sn x growth by using either B implantation or in situ Ga doping technique. In the B-implanted Ge 1− x Sn x formation case, fully strained B-doped Ge 1− x Sn x layers with no Sn precipitation can be obtained even after solid phase epitaxial regrowth (SPER). However, the serious dislocation generation in the layer was occurred during SPER. This is caused by the point defects introduced by B implantation. In order to avoid this crystal damage, we have also demonstrated in situ Ga-doped Ge 1− x Sn x growth. In this case, we can achieve fully strained Ga-doped Ge 1− x Sn x growth without Sn precipitation and any defect generation. Secondary, we have demonstrated the formation of Ni(Ge 1− y Sn y ) layers for metal/semiconductor contact and investigated the crystalline qualities. The formation of polycrystalline Ni(Ge 1− y Sn y ) layers on Ge 1− x Sn x layers with Sn contents ranging from 2.0% to 6.5% after annealing at from 350 °C to 550 °C can be achieved. Additionally, in the case of the Ni/Ge 1− x Sn x /Ge sample with a Sn content of 3.5%, an epitaxial Ni 2 (Ge 1− y Sn y ) layer on a Ge 1− x Sn x layer was formed. However, the surface roughness due to the agglomeration of Ni(Ge 1− x Sn x ) increases with increasing the Sn content and the annealing temperature. Therefore, a low thermal budget must be required for the formation of Ni(Ge 1− x Sn x ) with high Sn content.

The impact of different processing steps on the electrical properties of homo- and hetero-epitaxial junctions deposited on silicon substrates is described. In particular, the influence of the pre-epi in situ cleaning, using a high temperature bake in H2 is investigated. It is shown that the removal of oxygen and carbon from the starting surface is crucial in obtaining high-quality, low-leakage epitaxial junctions. In addition, it is demonstrated that post-epi implantation and anneal should be carefully optimized in order to maintain the strain in SiGe layers and to control the defect formation.

In this work, we report the selective area epitaxial growth of high quality InP in shallow trench isolation (STI) structures on Si (0 0 1) substrates 6° miscut toward (1 1 1) using a thin Ge buffer layer. We studied the impact of growth rates and steric hindrance effects on the nano-twin formation at the STI side walls. It was found that a too high growth rate induces more nano-twins in the layer and results in InP crystal distortion. The STI side wall tapering angle and the substrate miscut angle induced streric hindrance between the InP facets and the STI side walls also contribute to defect formation. In the [1 1 0] orientated trenches, when the STI side wall tapering angle is larger than 10°, crystal distortion was observed while the substrate miscut angle has no significant impact on the InP defect formation. In the [1 1 0] trenches, both the increased STI tapering angle and the substrate miscut angle induce high density of defects. With a small STI tapering angle and a thin Ge layer, we obtained extended defect free InP in the top region of the [1 1 0] trenches with aspect ratio larger than 2.

We report high quality InP layers selectively grown in shallow trench isolation structures on 6 degree offcut Si (001) substrates capped with a thin Ge buffer layer. The Ge layer was used to reduce the thermal budget for surface clean and double step formation. The atomic steps on the Ge surface were recovered after a bake at 680°C. Smooth nucleation layer was obtained at 420°C on the Ge surface. Baking the Ge surface in As ambient facilitates the InP nulceation and improves the InP crystalline quality. This improvement is attributed to the effective As adsorption on the Ge surface and the polar Ge:As surface prevents the islanding of InP seed layer. Stacking faults were found in the InP layers as a result of threading dislocation dissociation and high quality InP layers were obtained in trenches with aspect ratio greater than 2.

In this paper, we show the results of experiments of InAs nanowire (NW) growth on (111)-oriented Si wafers. The NWs, grown at 620 ° C by metal-organic vapor-phase epitaxy, are vertically aligned and ~30 nm in diameter. Their structural properties are studied by transmission electron microscopy, evidencing a polytypic character, and the vibrational properties by Raman spectroscopy. An assessment of their electrical transport properties is carried out by measuring back-gated, single InAs NW field-effect transistors. The absence of a catalyst ensures the compatibility of the NW growth process with current CMOS technology.

We have deposited III-V alloys on 200 mm Si miscut wafers with an oxide pattern. The selective epitaxial growth (SEG) of GaAs in large windows defined by SiO2 lines on a thick strained-relaxed Ge buffer layer served as a test vehicle which allowed us to demonstrate the integration of a III-V material deposition process step in a Si manufacturing line using an industrial reactor. High quality GaAs layers with high wafer-scale thickness uniformity were achieved. In a subsequent step, SEG of InP was successfully performed on wafers with a 300 nm shallow trench isolation pattern. The seed layer morphology depended on the treatment of the Ge surface and on the growth temperature. The orientation of the trench with respect to the substrate miscut direction had an impact on the quality of the InP filling. Despite of the challenges, such an approach for the integration of III-V materials on Si substrates allowed us to obtain extended-defect-free epitaxial regions suitable for the fabrication of high-performance devices.

Selective epitaxial growth of Ge films on Si substrates is a key technique for development of high-mobility monolithic MOSFETs with Ge channels alternative to conventional Si-based channels [1]. To date, many studies have been made on growing Ge films on Si substrates for blanket layers and large area devices by molecular beam epitaxy and chemical vapor deposition (CVD). A common subject for the growth of high-quality Ge films on Si(001) is controls of the density and distribution of dislocations which caused by strain relaxation at the Ge/Si interface with lattice mismatch of 4.2 %. In particular, 60° dislocations critically affect the crystallinity of Ge films. Various methods have been proposed to reduce the density of 60° dislocations in Ge layers grown on Si substrates. Besides the problems of dislocations, there is insufficient understanding of crystallinity and strain relaxation in micron-sized Ge films. The use of Si substrates with standard shallow trench isolation (STI) patterning by SiO2 is beneficial for selective growth of Ge films on Si substrates [1]. However, it is unclear the effects of SiO2 side walls on crystallinity and strain relaxation of Ge films on Si window areas. In this study, we investigated the crystallinity of micron-sized Ge thin films epitaxially grown on Si (001) substrates with mask patterns of SiO2 using X-ray microdiffraction (XRMD) [2].

Dichlorosilane (DCS), silane and trisilane have been investigated as Si precursors for low temperature ( 5 A/min). Trisilane permits the growth of Si at lower temperatures below 350 °C due to a specific growth mechanism enhancing H desorption. Layers grown at temperatures lower than 500 °C are defective, irrespective of the carrier gas, pressure and precursor flow used.

The rapid cadence of MOSFET scaling is stimulating the development of new technologies and accelerating the introduction of new semiconducting materials as silicon alternative. In this context, 2D materials with a unique layered structure have attracted tremendous interest in recent years, mainly motivated by their ultra-thin body nature and unique optoelectronic and mechanical properties. The development of scalable synthesis techniques is obviously a fundamental step towards the development of a manufacturable technology. Metal-organic chemical vapor deposition has recently been used for the synthesis of large area TMDs, however, an important milestone still needs to be achieved: the ability to precisely control the number of layers and surface uniformity at the nano-to micro-length scale to obtain an atomically flat, self-passivated surface. In this work, we explore various fundamental aspects involved in the chemical vapor deposition process and we provide important insights on the layer-dependence of epitaxial MoS2 film's structural properties. Based on these observations, we propose an original method to achieve a layer-controlled epitaxy of wafer-scale TMDs.

To further boost the CMOS device performance, Ge has been successfully integrated on shallow trench isolated Si substrates for pMOSFET fabrication. However, the high threading dislocation densities (TDDs) in epitaxial Ge layers on Si cause mobility degradation and increase in junction leakage. In this work, we studied the fabrication of Ge virtual substrates with low TDDs by Ge selective growth and high temperature anneal followed by chemical mechanical polishing (CMP). With this approach, the TDDs in both submicron and wider trenches were simultaneously reduced below 1 × 107 cm− 2 for 300 nm thick Ge layers. The resulting surface root-mean-square (RMS) roughness is about 0.15 nm. This fabrication scheme provides high quality Ge virtual substrates for pMOSFET devices as well as for III–V selective epitaxial growth in nMOSFET areas. A confined dislocation network was observed at about 50 nm above the Ge/Si interface. This dislocation network was generated as a result of effective threading dislocation glide and annihilation. The separation between the confined threading dislocations was found in the order of 100 nm.

We evaluated the combination of vapor phase doping and sub-melt laser anneal as a novel doping strategy for the fabrication of source and drain extension junctions in sub-32 nm CMOS technology, aiming at both planar and non-planar device applications. High quality ultra shallow junctions with abrupt profiles in Si substrates were demonstrated on 300 mm Si substrates. The excellent results obtained for the sheet resistance and the junction depth with boron allowed us to fulfill the requirements for the 32 nm as well as for the 22 nm technology nodes in the PMOS case by choosing appropriate laser anneal conditions. For instance, using 3 laser scans at 1300 °C, we measured an active dopant concentration of about 2.1 × 10 20 cm − 3 and a junction depth of 12 nm. With arsenic for NMOS, ultra shallow junctions were achieved as well. However, as also seen for other junction fabrication schemes, low dopant activation level and active dose (in the range of 1–4 × 10 13 cm − 2 ) were observed although dopant concentration versus depth profiles indicate that the dopant atoms were properly driven into the substrate during the anneal step. The electrical deactivation of a large part of the in-diffused dopants was responsible for the high sheet resistance values.

Low temperature epitaxial growth of group-IV alloys is a key process step to realize the advanced Si-based devices. In order to keep high growth rate below 600 °C, trisilane (Si 3 H 8 ) was used for their growth as an alternative Si precursor gas. Then, we compared the use of Si 3 H 8 versus SiH 4 for Si 1− x Ge x growth in H 2 and N 2 as carrier gas by low temperature chemical vapor deposition. By using Si 3 H 8 and controlling GeH 4 flow rate, Si 1− x Ge x growth with high growth rate and wide range of Ge concentration has been achieved compared to SiH 4 -based process. The growth rate and Ge concentration in Si 1− x Ge x with Si 3 H 8 grown at 600 °C ranged from 11 to 74 nm/min and from 0 to 40%, respectively. The obtained growth rates with Si 3 H 8 are between 1.5 and 6 times higher than for SiH 4 at a given growth condition. Si 3 H 8 -based in-situ B- and C-doped Si 1− x Ge x growth with high growth rate was also demonstrated.

Further improving CMOS performance beyond the 22 nm generation likely requires the use of high mobility channel materials. Complementary integration of different materials on Si can be realized with selective epitaxial growth. We present two fabrication schemes for Ge virtual substrates on standard Si STI wafers. This reduces the fabrication cost of these virtual substrates as it omits the complicated isolation scheme in blanket Ge. The low topography enables integration of ultra thin high-K gate dielectrics. The fabrication schemes are compatible with uni-axial stress techniques. Both modules include an anneal at 850 {degree sign}C to reduce the threading dislocation density down to 4x108 cm-2 and 1x107 cm-2, respectively. We are able to fabricate high quality Ge virtual substrates for pMOS devices as well as suitable starting surfaces for selective epitaxial III/V growth. The latter one will be illustrated by preliminary results of selective epitaxial InGaAs growth on virtual Ge substrates.

Several device concepts have been further evaluated after the successful implementation of epitaxial Si, SiGe and/or Si:C layers. Most of the next device generations will put limitations on the thermal budget of the deposition processes without making concessions on the epitaxial layer quality. In this work we address the impact of ex-situ wet chemical cleans and in-situ pre-epi bake steps, which are required to obtain oxide free Si surfaces for epitaxial growth. The combination of defect measurements, Secondary Ion Mass Spectroscopy, photoluminescence, lifetime measurements, and electrical diode characterization gives a very complete overview of the performance of low-temperature pre-epi cleaning methods. Contamination at the epi/substrate interface cannot be avoided if the pre-epi bake temperature is too low. This interface contamination is traceable by the photoluminescence and lifetime measurements. It may affect device characteristics by enhanced leakage currents and eventually by yield issues due to SiGe layer relaxation or other defect generation. A comparison of state of the art 200 mm and 300 mm process equipment indicates that for the same thermal budgets the lowest contamination levels are obtained for the 300 mm equipments.

In the first part of this work we studied the effect of annealing time and temperature on the degree of threading dislocations density (TDD) reduction in epitaxial Ge films grown by CVD on Si. We show, that one-step controlled nitrogen annealing at temperatures above 800 °C can decrease TDD of thick (1.6 µm) Ge layers with 1 order of magnitude from 1E+ 08/cm 2 down to 1E+ 07/cm 2 . Our results indicate that when temperature is high enough (> 800 °C) time does not play a role anymore. Thus for a temperature of 850 °C the same degree of TDD reduction can be achieved for 3 as well for 30 min. In the second part of the work we demonstrate that the combination of cycled epi growth and high temperature annealing although beneficial for TDD reduction deteriorates the crystalline quality of the layers due to significant Si out-diffusion and SiGe formation. Ge on Si substrates with lower defect densities have been further characterized by leakage current measurements on diode structures. Our results indicate that the reduction of drain to bulk leakage is insignificant and does not correspond to 1 order of magnitude reduction in TDD. We therefore conclude that threading dislocations are not the dominant factor for reduced device performance.

In the first part of this work, the fabrication of silicon germanium-on-insulator substrates (SGOI) by the Ge condensation technique was studied. Ge atomic fractions as high as 93% have been obtained while maintaining nice structural properties of the films. We show that these layers exhibit a large compressive strain and that the strain can be lowered by introducing some annealing steps in argon ambient during the condensation. SGOI substrates with a Ge atomic fraction of 75% were subsequently used as template for the growth of strained epitaxial Ge layers. Because of the important strain in the SGOI, the temperature for the in-situ bake prior to the growth has to be carefully selected in order to avoid relaxation. Ge layers with compressive strain up to −1% and thicknesses up to 40 nm have been obtained. The crystal quality, roughness and thermal stability of the strained Ge layers were finally evaluated.

Selective epitaxial growth of GaAs on Ge is a prerequisite for the integration of GaAs and Ge in the sub-22 nm CMOS nodes. The problems encountered for epitaxial growth of GaAs on Ge are described and illustrated. Mainly the problem of anti-phase boundary (APB) formation is addressed. Selective epitaxial growth of GaAs on Ge with a SiO 2 mask is discussed and selectively grown layers are characterized by X-ray diffraction, electron microscopy, defect etching and photoluminescence spectroscopy. An optimized growth procedure is presented, which simultaneously reduces loading effects and APB creation. Low temperature photoluminescence measurements show the good quality of the selectively grown GaAs on Ge.

Ge selective epitaxial growth (SEG) in shallow trench isolated windows is of great interest in advanced devices due to the good lateral electrical isolation of shallow trenches and the possibility of integrating Ge on Si wafers. However, the high density of threading dislocations in strain-relaxed Ge layers and facet formation are two major concerns in Ge SEG. In this work, we have obtained facet-free growth of Ge in shallow trench isolated Si windows with a threading dislocation density (TDD) of 4.2×108 cm-2. A mass transport model is developed to simulate the Ge faceting and the factors influencing the Ge deposition selectivity are studied.

We investigated the growth of in-situ n-type doped epitaxial Si layers with arsenic and phosphorus by means of low-temperature chemical vapor deposition using trisilane as Si-precursor. Indeed, in order to prevent the alteration of the characteristics of the devices which are already present on the wafer, an epitaxy process at low temperature is highly desired for applications such as BiCMOS. In this work, the varying parameters are the deposition temperature, the Si-precursor mass flow and the dopant gas flow. As a result, a process for the deposition of heavily doped epilayers was demonstrated at 600 °C with high deposition rate, which is important for maintaining high throughput and low process cost. We showed that using trisilane as a Si-precursor resulted in a much more linear n-type doping behavior than using dichlorosilane. Therefore it allowed an easier process control and a wider dynamic doping range. Our process is an interesting route for the epitaxy of a low-resistance emitter layer for bipolar transistor application.

The objective of this paper is to elucidate novel applications where the low frequency component of a background signal (haze) level of a wafer inspection tool can be used to qualitatively analyze different epitaxial processes. During initial epitaxial development cycles, a fast method of qualifying the growth runs is required. While SEM inspections can sub-sample the wafer, a semi-quantitative way of qualifying growth can be immensely helpful to quicken up the process. In this paper we monitor the epitaxial growth of Ge (heteroepitaxial) and SiGe strain relaxed buffer layers (SRB approach) with haze.

Fabrication of strained silicon on insulator (sSOI) substrates by wafer bonding and layer splitting is described in this paper. The sSi layer of 20 nm thickness is obtained on an 8 in. virtual substrate that consists of a plastically relaxed SiGe layer grown epitaxially on Si(0 0 1) by chemical vapor deposition (CVD). The plastic relaxation of the initially pseudomorphic SiGe layer is mediated by helium implantation into the Si wafer below the SiGe/Si(0 0 1) interface and subsequent annealing. A SiO 2 layer is grown by plasma enhanced (PE) CVD on the sSi/virtual substrate prior to wafer bonding. The PECVD oxide layer is used to compensate the thermal stress existing at the bonding interface during annealing. The SiO 2 /sSi/virtual substrate wafers are then implanted with hydrogen at a high dose (3.5 × 10 16 H 2 + cm −2 ) and subsequently bonded to Si(0 0 1) handle wafers. Subsequent annealing of the bonded wafer pair leads to the transfer of the implanted layer (containing the sSi layer) from the virtual substrate to the Si handle wafer. The final sSOI structure is realized by subsequent chemo-mechanical polishing followed by selective wet chemical etching. The sSOI substrate shows good thickness uniformity (∼20 nm) of the sSi layer over the entire 8 in. area and the strain measurements indicate a value of ∼0.66%.

We have selectively grown thin epitaxial GaAs films on Ge substrates with the aid of a 200 nm thin SiO2 mask layer. The selectively grown structures have lateral sizes ranging from 1 um width up to large areas of 1 by 1 mm2. The growth with the standard growth procedure for GaAs growth on Ge substrates reveals a limited amount of GaAs nucleation on the mask area and strong loading effects caused by diffusion of group III precursors over the mask area and in the gas phase. Reduction of the growth pressure inhibits GaAs nucleation on the mask area and reduces the loading effects strongly, but favors the creation of anti phase domains in the GaAs. An optimized growth procedure was developed, consisting of a 13 nm thin nucleation layer grown at high pressure, followed by low pressure growth of GaAs. This optimized growth procedure inhibits the nucleation of GaAs on the mask area and is a good compromise between reduction of loading effects and inhibition of anti phase domain growth in the GaAs. X-ray diffraction and photoluminescence measurements demonstrate the good microscopic characteristics of the selectively grown layers., Comment: 14 pages, 8 figures

We are reporting on a growth procedure for selective growth of GaAs on Ge substrates by organometallic vapor phase deposition. The precursors used for the growth are Tertiarybutylarsine (TBAs) and Trimethylgallium (TMGa). As a mask material 200 nm thick polycrystalline SiO2 was deposited on a 6° miscut Ge(001) substrate. The patterns available on the mask are various structures with feature sizes ranging from a fraction of a micron to a mm square. The filling factor of the mask, defined by the ratio of open area on the substrate to the area covered by SiO2, is approximately 2⁄3. This means that most of the wafer is covered with SiO2, making loading effects due to enhanced concentration of growth species at the mask openings very apparent. The most critical processing step during the selective growth of GaAs on Ge is the growth of the nucleation layer. This nucleation layer needs to be grown at high pressure in order to maximize the As partial pressure, which avoids formation of anti phase domains during the initial nucleation stages. Unfortunately, at high pressure, the nucleation of GaAs on the SiO2 is largest as well. As a result, during the initial growth steps, a small amount of GaAs is nucleated on the SiO2 area, which should be avoided. By keeping the high pressure nucleation layer as thin as possible and by reducing the pressure in the reactor as fast as possible, this nucleation can be avoided. A detailed study of the growth sequence for this nucleation layer has been undertaken, showing the tradeoff between thin high pressure nucleation layer and presence of anti-phase domains in the final selectively grown GaAs layer. Loading effects due to enhanced growth at the boundaries of the SiO2 layer are studied as well. Characterization of the material was done with X-ray diffraction, defect etching, cross-section scanning electron microscopy, photoluminescence spectroscopy and Nomarski microscopy. The final results show that the growth of high quality anti phase domain-free GaAs on Ge is possible, with no GaAs nucleation on the SiO2 mask material. A loading effect at the boundaries of the GaAs is still present and can not be eliminated with the present growth precursors. Figure 1: Nomarski microscope picture of a selectively grown GaAs structure on a 6° miscut Ge substrate. The mask material is a 200 nm thick SiO2 film.

Ultra-thin SiGe films on insulator with high Ge fraction were fabricated through Ge condensation. To achieve that strained Si0.75Ge0.25 layers were grown epitaxially on SOI wafers and oxidized in O2 at 1150ºC for various times. Raman measurements and X-TEM revealed the importance of purity of oxidation ambient for the oxidation process. Traces of moisture in the oxygen flux accelerate the process causing a switch from dry to wet oxidation mechanism, leading to complete oxidation of the starting layer in only 1 hour. The crystal quality and overall uniformity of such layers however is poor. The use of 100% dry oxygen provides the necessary control over the oxidation process. This allowed relaxed SiGe layers with concentration of Ge up to 45% and higher to be obtained. X-TEM indicated good crystalline quality and uniform layers with no threading dislocations or other defects introduced during oxidation.

Epitaxial fully strained Si films are known to form an effective passivation of the Ge(1 0 0) surface. However, we show using low-energy secondary ion mass spectrometry (SIMS) that considerable Ge surface segregation occurs for Si films grown from SiH 4 at 500 °C. In this study, we develop an alternative deposition process at 350 °C using Si 3 H 8 which significantly decreases the Ge peak at the Si surface. We attribute this strong reduction mainly to the fact that growth at 350 °C from trisilane proceeds below the Si–H desorption temperature. Charge pumping measurements on n-type Ge devices show a reduction by approximately a factor three in the high-k/substrate interface trap density for the samples with 350 °C Si passivation, compared to those using a Si passivation deposited at 500 °C.

Ultra-thin Si1−xGex films on insulator (SGOI) with high Ge fraction were fabricated through Ge condensation. To achieve that strained Si0.75Ge0.25 layers were grown epitaxially on a silicon-on-insulator (SOI) wafers and subsequently oxidized in O2 at 1150 °C for various times. Raman Spectroscopy as well as Cross-sectional Transmission Electron Microscopy (X-TEM) revealed that purity of oxidation ambient among other factors is very important for the oxidation process. Traces of moisture in the oxygen flux accelerated the process causing a switch from dry to wet oxidation mechanism, which resulted in complete oxidation of the starting layer in only 1 h. The crystal quality and overall uniformity of such a layer was poor. The use of 100% dry oxygen on the other hand provides the necessary control over the oxidation process. This allowed relaxed (strain 1% and below) Si1−xGex layers with concentration of Ge up to 47% and uniform Ge distribution to be obtained. X-TEM analysis indicated that the crystal quality of the layers, is good and no threading dislocations are introduced for strain relaxation during the oxidation process. Uniformity of the layers was good as revealed by Raman Spectroscopy and Cross-sectional Scanning Electron Microscopy (X-SEM).