1. A 28-Gb/s 4-Tap FFE/15-Tap DFE Serial Link Transceiver in 32-nm SOI CMOS Technology.
- Author
-
Bulzacchelli, John F., Menolfi, Christian, Beukema, Troy J., Storaska, Daniel W., Hertle, Jürgen, Hanson, David R., Hsieh, Ping-Hsuan, Rylov, Sergey V., Furrer, Daniel, Gardellini, Daniele, Prati, Andrea, Morf, Thomas, Sharma, Vivek, Kelkar, Ram, Ainspan, Herschel A., Kelly, William R., Chieco, Leonard R., Ritter, Glenn A., Sorice, John A., and Garlett, Jon D.
- Subjects
COMPLEMENTARY metal oxide semiconductors ,TRANSMITTERS (Communication) ,RADIO transmitters & transmission ,EQUALIZERS (Electronics) ,MOTHERBOARDS - Abstract
This paper presents a 28-Gb/s transceiver in 32-nm SOI CMOS technology for chip-to-chip communications over high-loss electrical channels such as backplanes. The equalization needed for such applications is provided by a 4-tap baud-spaced feed-forward equalizer (FFE) in the transmitter and a two-stage peaking amplifier and 15-tap decision-feedback equalizer (DFE) in the receiver. The transmitter employs a source-series terminated (SST) driver topology which doubles the speed of existing half-rate designs. The high-frequency boost provided by the peaking amplifier is enhanced by adopting a structure with capacitively coupled parallel input stages and active feedback. A capacitive level-shifting technique is introduced in the half-rate DFE which allows a single current-integrating summer to drive the four parallel paths used for speculating the first two DFE taps. Error-free signaling at 28 Gb/s is demonstrated with the transceiver over a channel with 35 dB loss at half-baud frequency. In a four-port core configuration, the power consumption at 28~Gb/s is 693 mW/lane. [ABSTRACT FROM PUBLISHER]
- Published
- 2012
- Full Text
- View/download PDF