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Linear block code (LBC) is an error detection and correction code that is widely used in communication systems. In this paper a special type of LBC called Hamming code was implemented and debugged using FPGA kit with integrated software environments ISE for simulation and tests the results of the hardware system. The implemented system has the ability to correct single bit error and detect two bits error. The data segments length was considered to give high reliability to the system and make an aggregation between the speed of processing and the hardware ability to be implemented. An adaptive length of input data has been consider, up to 248 bits of information can be handled using Spartan 3E500 with 43% as a maximum slices utilization. Input/output data buses in FPGA have been customized to meet the requirements where 34% of input/output resources have been used as maximum ratio. The overall hardware design can be considerable to give an optimum hardware size for the suitable information rate. [ABSTRACT FROM AUTHOR]

The pace of development of the microelectronic industry and the progress in the development of computer-aided design tools make problems associated with the development of combinational circuits that are resistant to short self-clearing faults relevant again. These faults occur due to a combination of many different factors, such as extreme operating conditions and transition to nanometer design standards. Structural redundancy methods are often used to solve this problem by the principles of the noiseless coding theory to protect information during its transmission over communication channels. However, these methods have a significant drawback, i.e., large structural redundancy. In this paper, we propose to use an approach based on the synthesis of fault-tolerant combinational circuits based on the spectral R-code to solve the problem of developing fault tolerant combinational circuits. If a specific part of the coder is protected using special technological means, this code can correct a single-bit error and detect a double-bit error. The resulting circuit has less structural redundancy compared to the traditional method of triple modular redundancy (TMR). An approach is also proposed based on partitioning circuit outputs into groups followed by synthesizing fault-tolerant combinational circuits based on the R-code, which increases the probability of error detection/correction, to minimize the probability of multiple-bit errors within a combinational circuit. The paper presents the results of a series of numerical experiments that show the efficiency of the proposed approaches. [ABSTRACT FROM AUTHOR]

In recent years, there has been a growing interest in codes that can correct adjacent bit errors in memories. This is due to the increasing percentage of radiation induced errors that affect multiple cells due to technology scaling. The cells affected by the errors are physically close and in many cases adjacent. This means that in the absence of interleaving, adjacent bits will be likely to be affected by an error. A number of Single Error Correction and Double Adjacent Error Correction (SEC-DAEC) codes have been proposed to deal with those errors. These codes have a low overhead in terms of number of additional parity check bits compared to Double Error Correction (DEC) codes. A problem is that they can introduce a significant penalty in terms of delay compared to a Single Error Correction (SEC) or a Single Error Correction and Double Error Detection (SEC-DED) code. This is due to the more complex decoding that needs to check approximately twice the number of syndrome patterns. In this paper, low delay SEC-DAEC codes are presented and the parity check matrices for 16, 32 and 64 bit data words are provided. To reduce the delay, a number of techniques are used in the construction of the code and in the implementation of the decoder. The evaluation shows that this results in significant savings compared to existing SEC-DAEC codes. Therefore, the proposed codes can be useful for high speed designs on which adjacent error correction is required. [ABSTRACT FROM AUTHOR]

In this paper, we introduce a new complex Fibonacci matrix H p , n whose elements are complex Fibonacci numbers and we developed a new coding and decoding method followed from this complex Fibonacci matrix H p , n . We establish the relations among the code matrix elements, error detection and correction for this coding theory. [ABSTRACT FROM AUTHOR]

Additional check bits, which are commonly attached to the message’s input data, are normally used to minimize the error during data transmission. The receiver system implements a checking algorithm to determine if an error was occurred in the received data. This algorithm will correct a corrupted bit and recover the original message. An enhanced error detection correction code was presented to better detect and correct the corrupted conveyed bits. It improves the existing limitations of utilizing cyclic redundancy checking (CRC), Hamming code, and other checksum techniques. Also, it reduced the length of the redundancy bits which exists in CRC, the overhead of interspersing of the redundancy bits in a typical Hamming code, and the system resources such as processor time and bandwidth in checksum techniques. This paper was synthesized and simulated using the Xilinx Spartan 6 (XC7Z020-2CLG4841) FPGA. Results show that the resource utilization of the designed memory architecture using EEDC is lower compared to CRC, Hamming, and Checksum algorithms. [ABSTRACT FROM AUTHOR]

Transforming error-prone immunosequencing datasets into Ab repertoires is a fundamental problem in immunogenomics, and a prerequisite for studies of immune responses. Although various repertoire reconstruction algorithms were released in the last 3 y, it remains unclear how to benchmark them and how to assess the accuracy of the reconstructed repertoires. We describe an accurate IgReC algorithm for constructing Ab repertoires from high-throughput immunosequencing datasets and a new framework for assessing the quality of reconstructed repertoires. Surprisingly, Ab repertoires constructed by IgReC from barcoded immunosequencing datasets in the blind mode (without using information about unique molecular identifiers) improved upon the repertoires constructed by the state-of-the-art tools that use barcoding. This finding suggests that IgReC may alleviate the need to generate repertoires using the barcoding technology (the workhorse of current immunogenomics efforts) because our computational approach to error correction of immunosequencing data is nearly as powerful as the experimental approach based on barcoding. [ABSTRACT FROM AUTHOR]

The design and implementation of an error detection and correction scheme in a MODBUS-RTU network based on the REED-SOLOMON code is presented. The transmission of the parity bits is made respecting the parameters of the MODBUS protocol, so the bus can be used by common devices without the error detection/correction scheme. The error detection–correction is performed by means of specialized repeating devices in the receiver and transmitter. This method respects the parameters of the MODBUS-RTU protocol, so the bus enhanced with retransmitter devices can be used along with common devices. Finally, the implementation of an experimental network is described and the practical results obtained are given. [ABSTRACT FROM AUTHOR]

. The study reported in this paper investigated the repair distribution, the error correction rates and the repair successfulness in the speech of L2 learners, with the goal to find out more information on the monitoring skills and repair behaviour. The research also included a detailed subcategory analysis within syntactic, lexical and morphological categories which have not been investigated so far. The lowest correction rates were observed in the case of morphological subcategories, showing that the speakers' attention was not oriented towards grammatical accuracy. The findings of this study may find practical application in foreign language teaching, suggesting possible reviews of formal teaching methods, aiming at more efficient linking of grammatical development to the ability to communicate. [ABSTRACT FROM AUTHOR]

Shortening is a widely used technique aiming mainly to reduce the block size of an error correcting code and at the same time to enhance its efficiency. However, due to a common misapprehension, students tend to believe that maximum shortening retains maximum coding efficiency. In this work, an educational approach is presented which eliminates the aforementioned misapprehension. Specifically, the efficiency of the shortened error correcting codes is examined both theoretically and experimentally via simulations [ABSTRACT FROM AUTHOR]

In many applications, an incoming value is compared against one or more values stored in registers. To avoid data corruption, the registers are in some cases protected with a single error correction (SEC) code. Therefore, in a traditional implementation, SEC decoding would be done before the comparison. However, previous works have shown that it may be more efficient to compare the SEC encoded values directly using a distance one comparison. This distance one comparison prevents single bit errors from affecting the result of the comparison and is in many cases simpler than an SEC decoding plus a traditional comparison. It is shown that the use of single-error correction double error detection (SEC-DED) encoded registers enables a simplified distance one comparison that can further reduce the cost of implementing error protection for register comparison. [ABSTRACT FROM AUTHOR]