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The pace of development of the microelectronic industry and the progress in the development of computer-aided design tools make problems associated with the development of combinational circuits that are resistant to short self-clearing faults relevant again. These faults occur due to a combination of many different factors, such as extreme operating conditions and transition to nanometer design standards. Structural redundancy methods are often used to solve this problem by the principles of the noiseless coding theory to protect information during its transmission over communication channels. However, these methods have a significant drawback, i.e., large structural redundancy. In this paper, we propose to use an approach based on the synthesis of fault-tolerant combinational circuits based on the spectral R-code to solve the problem of developing fault tolerant combinational circuits. If a specific part of the coder is protected using special technological means, this code can correct a single-bit error and detect a double-bit error. The resulting circuit has less structural redundancy compared to the traditional method of triple modular redundancy (TMR). An approach is also proposed based on partitioning circuit outputs into groups followed by synthesizing fault-tolerant combinational circuits based on the R-code, which increases the probability of error detection/correction, to minimize the probability of multiple-bit errors within a combinational circuit. The paper presents the results of a series of numerical experiments that show the efficiency of the proposed approaches. [ABSTRACT FROM AUTHOR]

We present new constructions of codes for asymmetric channels for both binary and nonbinary alphabets, based on methods of generalized code concatenation. For the binary asymmetric channel, our methods construct nonlinear single-error-correcting codes from ternary outer codes. We show that some of the Varshamov–Tenengol’ts–Constantin–Rao codes, a class of binary nonlinear codes for this channel, have a nice structure when viewed as ternary codes. In many cases, our ternary construction yields even better codes. For the nonbinary asymmetric channel, our methods construct linear codes for many lengths and distances which are superior to the linear codes of the same length capable of correcting the same number of symmetric errors. [ABSTRACT FROM AUTHOR]

Generalized balanced tournament packings (GBTPs) extend the concept of generalized balanced tournament designs introduced by Lamken and Vanstone (1989). In this paper, we establish the connection between GBTPs and a class of codes called equitable symbol weight codes (ESWCs). The latter were recently demonstrated to optimize the performance against narrowband noise in a general coded modulation scheme for power line communications. By constructing classes of GBTPs, we establish infinite families of optimal ESWCs with code lengths greater than alphabet size and whose narrowband noise error-correcting capability to code length ratios do not diminish to zero as the length grows. [ABSTRACT FROM AUTHOR]

We propose a method for improving noise immunity in data transmission channels for telemetry information systems by providing double byte data error correction with minimal time delay. [ABSTRACT FROM AUTHOR]

. The study reported in this paper investigated the repair distribution, the error correction rates and the repair successfulness in the speech of L2 learners, with the goal to find out more information on the monitoring skills and repair behaviour. The research also included a detailed subcategory analysis within syntactic, lexical and morphological categories which have not been investigated so far. The lowest correction rates were observed in the case of morphological subcategories, showing that the speakers' attention was not oriented towards grammatical accuracy. The findings of this study may find practical application in foreign language teaching, suggesting possible reviews of formal teaching methods, aiming at more efficient linking of grammatical development to the ability to communicate. [ABSTRACT FROM AUTHOR]

In many applications, an incoming value is compared against one or more values stored in registers. To avoid data corruption, the registers are in some cases protected with a single error correction (SEC) code. Therefore, in a traditional implementation, SEC decoding would be done before the comparison. However, previous works have shown that it may be more efficient to compare the SEC encoded values directly using a distance one comparison. This distance one comparison prevents single bit errors from affecting the result of the comparison and is in many cases simpler than an SEC decoding plus a traditional comparison. It is shown that the use of single-error correction double error detection (SEC-DED) encoded registers enables a simplified distance one comparison that can further reduce the cost of implementing error protection for register comparison. [ABSTRACT FROM AUTHOR]