Search

We report high-performance amorphous Indium-Gallium-Zinc-Oxide nanowire field-effect transistors ($\alpha $ -IGZO NW-FETs) featuring an ultrascaled nanowire width (${W}_{{\mathrm {NW}}}$) down to ~20 nm. The device with 100 nm channel length (${L}_{{\mathrm {CH}}}$) and ~25 nm ${W}_{{\mathrm {NW}}}$ achieves a decent subthreshold swing (SS) of 80 mV/dec as well as high peak extrinsic transconductance (${G}_{m,{\mathrm {ext}}}$) of $612~\mu S/\mu \text{m}$ at a drain–source voltage (${V}_{{\mathrm {DS}}}$) = 2 V ($456~\mu S/\mu \text{m}$ at ${V}_{{\mathrm {DS}}}$ = 1 V). The good electrical properties are enabled by using an ultrascaled 5 nm high- ${k}$ HfO2 as the gate dielectric, a water-free ozone-based atomic layer deposition (ALD) process, and a novel digital etch (DE) technique developed for indium-gallium-zinc-oxide (IGZO) material. By using low-power BCl3-based plasma treatment and isopropyl alcohol (IPA) rinse in an alternating way, the DE process is able to realize a cycle-by-cycle etch with an etching rate of ~1.5 nm/cycle. The scaling effects on device performance have been analyzed as well. It shows that the downscaling of ${W}_{{\mathrm {NW}}}$ improves the SS notably without sacrificing ON-state performance, and the shrinking of ${L}_{{\mathrm {CH}}}$ boosts the ${G}_{m,{\mathrm {ext}}}$. The ultrascaled $\alpha $ -IGZO NW-FETs could play an important role in applications where high performance and high density are highly desired. [ABSTRACT FROM AUTHOR]

We investigate the effect of channel layer thickness on effective mobility (μeff) in the sub-10-nm regime of amorphous indium–gallium–zinc–oxide thin-film transistors (α-IGZO TFTs). TFT devices with extremely scaled channel thickness tα-IGZO of 3.6 nm were realized, exhibiting low subthreshold swing (SS) of 74.4 mV/decade and the highest effective mobility μeff of 34 cm2/V ⋅ s at a carrier density NCarrier of ~ 5 × 1012 cm−2 for any kind of α-IGZO TFTs having sub-10-nm tα-IGZO. No significant degradation of μeff is observed as α-IGZO thickness reduced from 6 to 3.6 nm. By scaling down the channel length LCH to 38 nm, high extrinsic transconductance (Gm, max) of 125 μs/μm (at VDS of 1 V) and ON-state current ION of 350 μA/μm at VGS – VT of 3 V with VDS of 2.5 V are achieved. [ABSTRACT FROM AUTHOR]

A mechanically foldable and stretchable filter with stable filtering performance is presented in this letter. The filter is manufactured with liquid metal injected into microfluidic channels, which are realized in material of polydimethylsiloxane using soft lithography. The elastic dielectric material and liquid metal enable the deformation capability and mechanical stability of the filter along any direction. Frequency response, insertion loss, and return loss of the bended and stretched filters are investigated and compared with their original state through simulations and experiments. The fabricated filter demonstrates an insertion loss of 1.3 dB at the center frequency of 2.1 GHz and a return loss better than 10 dB over 1.6–2.6 GHz, and the overall filter size is 33 mm $\times25.3$ mm. Experiments verify that stretching up to 20% and bending with radii of 8.5 and 11.5 mm are possible with maintained electrical specifications. [ABSTRACT FROM PUBLISHER]

This paper presents a new integration scheme to fabricate a Si/Si0.55~Ge0.45 heterojunction line tunnel field effect transistor (TFET). The device shows an increase in tunneling current with gate length. The 1-\mum gate length device shows on current in excess of 20 \muA/\mum at VGS=VDS=1.2~\rm V. Low-temperature measurements, performed to suppress trap-assisted tunneling (TAT), reveal the point subthreshold swing as low as 22 mV/dec at 78 K. Field-induced quantum confinement effects are found to increase the tunneling onset voltage by \sim0.35~V. Variation of the tunneling onset voltage measured experimentally is correlated to variation in the pocket thickness and its doping concentration. Small geometry devices were found to be more susceptible to microvariations in the pocket thickness and doping concentration. [ABSTRACT FROM AUTHOR]

The role of trap-assisted tunneling (TAT) in the degradation of the subthreshold swing (SS) in n-type line tunnel field-effect transistors (TFETs) is investigated through the experiments and simulations. A two to fourfold increase in the interface state density is achieved by applying a positive or a negative stress between the gate and the source. The negative stress shows no impact on the SS in spite of nearly fourfold increase in the interface state density. A nearly twofold increase in interface state density and improvement in SS are observed under the application of positive stress. The improvement in SS is attributed to H^+ species released from the Si/SiO2 interface during stress, which moves toward the bulk Si, passivating boron and bulk Si traps, thereby improving the SS. Under negative stress bias, the released H^+ species drifts toward the gate electrode, and hence no change in SS was observed. These experiments suggest that the SS degradation is mainly caused by TAT through bulk Si traps and insensitive to interface traps. A good control of bulk semiconductor trap density will be required to achieve sub-60-mV/decade SS in line TFETs. [ABSTRACT FROM PUBLISHER]