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Fault-tolerant minimal routing algorithms aim at finding a Manhattan path between the source and destination nodes and route around all faulty nodes. Additionally, some non-faulty nodes that are helpless to make up of a fault-tolerant minimal path should also be routed around. How to label such non-faulty nodes efficiently is a major challenge. State-of-the-art solutions could not address it very well. We propose a path-counter method. It can label every node that are helpless to make up of a fault-tolerant minimal path with low time complexity. By counter the number of fault-tolerant minimal paths, it can: support arbitrary fault distribution, check the existence of fault-tolerant minimal paths, not sacrifice any available fault-tolerant minimal paths. [ABSTRACT FROM AUTHOR]

3D ICs can take advantage of a scalable communication platform, commonly referred to as the Networks-on-Chip (NoC). In the basic form of 3D-NoC, all routers are vertically connected. Partially connected 3D-NoC has emerged because of physical limitations of using vertical links. Routing is of great importance in such partially connected architectures. A high-performance, fault-tolerant and adaptive routing strategy with respect to the communication flow among the cores is crucial while freedom from livelock and deadlock has to be guaranteed. In this paper we introduce a new routing algorithm for partially connected 3D-NoCs. The routing algorithm is adaptive and tolerates the faults on vertical links as compared to the predesigned routing algorithms. Our results show a $40-50\%$ improvement in the fraction of intact inter-level communications when the fault tolerant algorithm is used. This routing algorithm is light-weight and has only one virtual channel along the $Y$ dimension. [ABSTRACT FROM AUTHOR]

Abstract: Adaptive routing algorithms have been employed in interconnection networks to improve network throughput and provide better fault tolerance characteristics. However, they can harm performance by disturbing any inherent global load balance through greedy local decisions. This paper proposes a novel scalable load balancing congestion-aware Network-on-Chip (NoC) architecture that not only enhances network transmission performance while maintaining a feasible implementation cost, but also improves overall network throughput for various traffic scenarios. This congestion control scheme which consists of dynamic input arbitration and adaptive routing path selection is proposed to balance global traffic load distribution so as to alleviate congestion caused by heavy network activities. Furthermore, faulty links information can be broadcasted by existing congestion management control signals to prevent packets from routing through defected areas in order to eliminate potential heavy congestion situations around these regions. Experimental results show that throughput is improved dramatically while maintaining superior latency performance for various traffic patterns. Compared to a baseline router, the proposed congestion management mechanism requires negligible cost overhead but provides better throughput for both mesh and diagonally-linked mesh NoC platforms. [Copyright &y& Elsevier]