1. A Defect Tolerance Scheme for Nanotechnology Circuits.
- Author
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Al-Yamani, Ahmad A., Ramsundar, Sundarkumar, and Pradhan, Dhiraj K.
- Subjects
- *
ELECTRONICS , *DIGITAL electronics , *HIGH technology , *LITHOGRAPHY , *ELECTRONIC circuits , *NANOTECHNOLOGY , *ALGORITHMS , *NANOWIRES , *NANOSTRUCTURED materials - Abstract
Lithography-based integrated circuit fabrication is rapidly approaching its limit in terms of feature size. The current alternative is nanotechnology-based fabrication, which relies on self-assembly of nanotubes or nanowires. Such a process is subject to a high defect rate, which can be tolerated using carefully crafted defect tolerance techniques. This paper presents an algorithm for reconfiguration-based defect tolerance in nanotechnology switches. The algorithm offers an average switch density improvement of 50% to 100% to most recently published techniques. The algorithm is also consistent in improving the yield through minimizing false rejects as the results show over a large sample. The improvement percentage varies depending on the manufactured switch size and the desired defect-free size with the improvement in efficiency directly proportional to the size of the switch. [ABSTRACT FROM AUTHOR]
- Published
- 2007
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