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Safety-critical embedded systems must maintain their functionality even in the presence of single permanent hardware failure. Naive redundancy of hardware is often unaffordable and impractical, therefore alternative strategies must be explored for minimal cost fault tolerance. The objective of this article is to propose a methodology to evaluate formally safety strategies using satisfiability modulo theory solvers. Practically, the approach consists in providing a bounded model checking demonstration applied to the formal model of hardware. We show the capabilities of the approach on an efficient hardware accelerator designed to perform parallel computations of matrix multiplications and convolutions. [ABSTRACT FROM AUTHOR]

Due to the growing complexity of modern data centers, failures are not uncommon any more. Therefore, fault tolerance mechanisms play a vital role in fulfilling the availability requirements. Multiple availability models have been proposed to assess compute systems, among which Bayesian network models have gained popularity in industry and research due to its powerful modeling formalism. In particular, this work focuses on assessing the availability of redundant and replicated cloud computing services with Bayesian networks. So far, research on availability has only focused on modeling either infrastructure or communication failures in Bayesian networks, but have not considered both simultaneously. This work addresses practical modeling challenges of assessing the availability of large‐scale redundant and replicated services with Bayesian networks, including cascading and common‐cause failures from the surrounding infrastructure and communication network. In order to ease the modeling task, this paper introduces a high‐level modeling formalism to build such a Bayesian network automatically. Performance evaluations demonstrate the feasibility of the presented Bayesian network approach to assess the availability of large‐scale redundant and replicated services. This model is not only applicable in the domain of cloud computing it can also be applied for general cases of local and geo‐distributed systems. [ABSTRACT FROM AUTHOR]

This paper applies basic swarm robotics concepts to the control of a redundant multi-source power supply system for an automotive onboard grid. The fundamental concepts and thoughts are explained to give a basic understanding of swarm robotics engineering, redundant vehicle power system structures, DC-DC converter modeling and control. A simplified example application is modeled and simulated as a first proof of concept. The results show the feasibility of the artificial swarm intelligence based concept. The numerical assessment shows significant improvements in dynamic control quality, bandwidth, stability, robustness and fault tolerance without the need for additional dedicated communication compared to a traditional single-source solution. In a second simulation, an adaptive and fault tolerant PWM carrier shift optimization is successfully realized. This demonstrates an even more advanced technical feature in addition to a pure high-stability voltage regulation and gives an outlook to the new possibilities opened up by applying swarm robotics concepts.

This work presents a study on the reliability of voters for approximate fault tolerant systems in the context of single event effects and electromagnetic interference. A first case study analyses different topologies of single-bit majority voters for logic circuits employing fault injection by simulation. In these simulations, an analysis is first performed to identify the critical diffusion areas of the physical implementation according to the voter input vector. Additionally, as a second case study, practical heavy ion experiments on different architectures of software-based approximate voters for mixed-signal applications are also presented, and the cross section of each voter is evaluated. The system comprising the voters was irradiated in two distinct experiments with an 16 O ion beam, producing an effective LET at the active region of 5.5 MeV/mg/cm 2 . As a complementary study, a conducted electromagnetic interference injection was also performed, considering two distinct voting schemes. Results of the case-studies allow identifying the most tolerant voter architectures (among the studied ones) for approximate computing applications under single event effects and electromagnetic interference. [ABSTRACT FROM AUTHOR]

Electronic circuits/systems operating in harsh environments such as space are likely to experience faults or failures due to the impact of high-energy radiation. Given this, to overcome any faults or failures, redundancy is usually employed as a hardening-by-design approach. Moreover, low power and a small silicon footprint are also important considerations for space electronics since these translate into better energy efficiency, less system weight, and less cost. Therefore, the fault-tolerant design of electronic circuits and systems should go hand in hand with the optimization of design metrics, especially for resource-constrained electronics such as those used in space systems. A single circuit or system (also called a simplex implementation) is not fault-tolerant as it may become a single point of failure and is not used for a space application. As an alternative, a triple modular redundancy (TMR) implementation, which uses three identical copies of a circuit or system and a voter to perform majority voting of the circuits and systems outputs, may be used. However, in comparison with a simplex implementation, a TMR implementation consumes about 200% more area and dissipates 200% more power when circuits or systems are triplicated. To mitigate the area and power overheads of a TMR implementation compared to a simplex implementation, researchers have suggested alternative redundancy approaches such as selective TMR (STMR) insertion, partially approximate TMR (PATMR), fully approximate TMR (FATMR), and majority voting-based reduced precision redundancy (VRPR). Among these, VRPR appears to be promising, especially for inherently error-tolerant applications such as digital image/video/audio processing, which is relevant to space systems. However, the alternative redundancy approaches mentioned are unlikely to be suitable for the implementation of control logic. In this work, we analyze various redundancy approaches and evaluate the performance of TMR and VRPR for a digital image processing application. We provide MATLAB-based image processing results corresponding to TMR and VRPR and physical implementation results of functional units based on TMR and VRPR using a 28-nm CMOS technology. [ABSTRACT FROM AUTHOR]

The purpose of the article is to develop and verify with the help of mathematical modeling a software method of deploying a fault-tolerant computing cluster with a virtual machine, which consists of two physical servers (main and backup), on which a distributed data storage system with synchronous data replication from the source server to the backup server is deployed. For this purpose, the task is to conduct a computational experiment on a model of a fault-tolerant cluster, which neglects costs during recovery for the migration of virtual machines by means of the mathematical application Mathcad. Combining computing resources into clusters is a way to ensure high reliability, fault tolerance, and continuity of the computing process of computer systems. This is achieved through virtualization, which enables the movement of virtual resources, services, or applications between physical servers while maintaining the continuity of computing processes. The focus of this study is on a failover cluster, which is composed of two physical servers (primary and backup) connected through a switch, and each server has a local hard disk. A distributed storage system with synchronous data replication from the source server to the backup server is deployed on the local disks of the servers, and a virtual machine is running on the cluster. Markovian processes, flows of podias, and Kolmogorov's systems of differential equations are built into the mathematical tools of the model of a water cluster. To ensure the continuity of the computing process in case of a failure of the main server, a shadow copy of the virtual machine is launched on the backup server. The reliability of the failover cluster is measured by the coefficient of non-stationary readiness. A Markov model is proposed to assess the reliability of the failover cluster, taking into account the costs of migrating virtual machines and mechanisms that ensure the continuity of the computing process in the cluster in case of a failure of one physical server. The memory migration process maintains two copies of the virtual machine on different physical servers, enabling them to continue working on the other in the event of failure. A simplified model of the failover cluster neglects the cost of migrating virtual machines and provides an upper estimate of reliability. The study shows that the reliability of a failover cluster, as measured by the non-stationary availability factor, is significantly impacted by the virtual machine migration process. The findings of this study can be used to inform decisions about the technology chosen to ensure the failure stability and continuity of the computing process of computer systems with cluster architecture. The calculations allow us to draw a conclusion about the significant impact of virtual machine migration accounting on reliability. The calculations allow us to draw a conclusion about the significant impact of virtual machine migration accounting on reliability. The calculation was performed under the following failure rates of the server, disk, and switch: λ0 = 1,115×10-5 1/h, λ1 = 3,425×10-6 1/h, λ2 = 2,3×10-6 1/h recovery respectively: μ0 = 0,33 1/h, μ1 = 0,171/h, μ2 = 0,33 1/h. The intensity of synchronization of the distributed storage system: μ3 = 1 1/h, μ4 = 2 1/h. The difference of non-stationary cluster availability coefficients is d = К2(t) – К1(t) = 2.7×10-10

Time-sensitive networking (TSN) is an industry-standard networking protocol that is widely deployed in safety-critical industrial and automotive networks thanks to its quality-of-service (QoS) mechanisms, esp. deterministic transmission and bounded end-to-end delay for time-triggered (TT) flows. In this article, we focus on TT flows and address the issue of fault tolerance against permanent and transient faults with both spatial and temporal redundancy. We present an efficient heuristic algorithm for online incremental rerouting and rescheduling of disrupted flows, assuming the paths and schedules of existing flows stay fixed. It is complementary to and can be combined with offline routing and scheduling algorithms for achieving fault tolerance based on frame replication and elimination for reliability (FRER) (IEEE 802.1CB). Performance evaluation shows that our approach is able to better recover the system’s degree of redundancy (DoR) and has a higher acceptance rate than related work. [ABSTRACT FROM AUTHOR]

Here, we propose a fault-tolerant workflow scheduling algorithm that combines basic redundancies to reduce execution time through minimizing the redundancy overhead. We propose a graph-theory-based divide and conquer approach for selecting fault-tolerance strategies for workflow tasks. The appropriate strategy for each task is determined with respect to runtime situation and the position of the task in the graph. The main idea of the proposed algorithm is that resources are apportioned among concurrently executing tasks such that more replicas are assigned to tasks that benefit more from having extra replicas. We use the concept of concurrency graph for finding idle durations of resources which are used for processing additional task replicas. We also propose an opportunistic method for executing extra replicas of tasks in situations that some resources become idle. Furthermore, we propose a new mapping order scheme for ordering task replicas on resources. The proposed approach achieves a significant performance improvement over the existing approaches especially in situations where few resources are enrolled with the aim of cost reduction. [ABSTRACT FROM AUTHOR]

In three-dimensional integrated circuits (3D-ICs), through silicon via (TSV) is a critical technique in providing vertical connections. However, yield is one of the key obstacles to adopt the TSV-based 3D-ICs technology in the industry. Various fault-tolerance structures using redundant TSVs to repair faulty functional TSVs have been proposed in the literature for yield and reliability enhancement. However, the TSV repair paths under delay constraint cannot always be generated due to the lack of appropriate repair algorithms. In this article, we propose an effective TSV repair strategy for the router-based TSV redundancy architecture, taking into account the delay overhead. First, we prove that the router-based fault-tolerance structure configuration (RFSC) with the delay constraint is equivalent to the length-bounded multicommodity flow (LBMCF) problem. Then, an integer linear programming (ILP) formulation with acceptable scalability is presented to solve the LBMCF problem. The experimental results demonstrate that, compared with state-of-the-art fault-tolerance designs, the proposed ILP model can provide higher yield and lower delay overhead. [ABSTRACT FROM AUTHOR]

Hardware faults on the regular 2-D computing array of a typical deep learning accelerator (DLA) can lead to dramatic prediction accuracy loss. Prior redundancy design approaches typically have each homogeneous redundant processing element (PE) to mitigate faulty PEs for a limited region of the 2-D computing array rather than the entire computing array to avoid the excessive hardware overhead. However, they fail to recover the computing array when the number of faulty PEs in any region exceeds the number of redundant PEs in the same region. The mismatch problem deteriorates when the fault injection rate rises and the faults are unevenly distributed. To address the problem, we propose a hybrid computing architecture (HyCA) for fault-tolerant DLAs. It has a set of dot-production processing units (DPPUs) to recompute all the operations that are mapped to the faulty PEs despite the faulty PE locations. According to our experiments, HyCA shows significantly higher reliability, scalability, and performance with less chip area penalty when compared to the conventional redundancy approaches. Moreover, by taking advantage of the flexible recomputing, HyCA can also be utilized to scan the entire 2-D computing array and detect the faulty PEs effectively at runtime. [ABSTRACT FROM AUTHOR]

Industrial and physical site information is sent to the monitoring center by sensors in wireless sensor networks so that they can easily control the process of a company in order to improve the optimal performance of the system until the failure occurs to monitor and control in wireless sensor networks. Sensors are exposed to a wide range of failures, possible hardware and software problems in normal conditions, extreme weather conditions or other conditions caused by harsh physical environment in the field of sensors. Therefore, there is a possibility of unpredictable failure for all types of sensors and with Industrial process monitoring, preventive status monitoring, prevented error and fault and failures. The focus of this article is to present a new architecture in improving the correct performance of the system, the replacement rate of more damaged nodes and timely replacement, at the time of the starting point of the failure, the main sensor with spare ones or healthy sensors with faulty ones. The proposed network structure is such that the spare node is placed in parallel with the main node; this method makes it possible for the spare node to be replaced in case of failure of the main node, and the failed node can be quickly repaired and put in a standby mode. Our proposed model is analyzed in terms of the average time of correct system operation until failure known as mean time to failure. In this article is presented and studied and evaluated, a new architecture to improve network performance against failure using Markov model and state probability, and mean failure rate for node fault tolerance, before failure with timely replacement in wireless sensor network. In the proposed architecture, the results show a better improvement of the system's correct performance in order to reduce the adverse effects of errors and failures and improve fault tolerance. The simulation results show that the advantage of using this method reduces the adverse effects of errors and failures and improves the optimal performance of the system in the industrial site. [ABSTRACT FROM AUTHOR]

Electronic circuits/systems operating in harsh environments such as space are likely to experience faults or failures due to the impact of high-energy radiation. Given this, to overcome any faults or failures, redundancy is usually employed as a hardening-by-design approach. Moreover, low power and a small silicon footprint are also important considerations for space electronics since these translate into better energy efficiency, less system weight, and less cost. Therefore, the fault-tolerant design of electronic circuits and systems should go hand in hand with the optimization of design metrics, especially for resource-constrained electronics such as those used in space systems. A single circuit or system (also called a simplex implementation) is not fault-tolerant as it may become a single point of failure and is not used for a space application. As an alternative, a triple modular redundancy (TMR) implementation, which uses three identical copies of a circuit or system and a voter to perform majority voting of the circuits and systems outputs, may be used. However, in comparison with a simplex implementation, a TMR implementation consumes about 200% more area and dissipates 200% more power when circuits or systems are triplicated. To mitigate the area and power overheads of a TMR implementation compared to a simplex implementation, researchers have suggested alternative redundancy approaches such as selective TMR (STMR) insertion, partially approximate TMR (PATMR), fully approximate TMR (FATMR), and majority voting-based reduced precision redundancy (VRPR). Among these, VRPR appears to be promising, especially for inherently error-tolerant applications such as digital image/video/audio processing, which is relevant to space systems. However, the alternative redundancy approaches mentioned are unlikely to be suitable for the implementation of control logic. In this work, we analyze various redundancy approaches and evaluate the performance of TMR and VRPR for a digital image processing application. We provide MATLAB-based image processing results corresponding to TMR and VRPR and physical implementation results of functional units based on TMR and VRPR using a 28-nm CMOS technology.

The torque ripple of a switched reluctance motor (SRM) should be taken into account, as it can have negative effects on a connected gearbox and/or load. In this paper a concept and two realization methods for the reduction of the torque ripple are presented. An optimized alignment of the active elements of the stator leads to a reduction of this torque ripple. The first method proposed here is a four-fold segmented motor, which can reduce the torque ripple by 37.3 %. This can be achieved by segmentation in combination with a clever arrangement of active elements. However, this increases the number of necessary inverters, which increases redundancy and therefore leads to more security. A second method of achieving an equal reduction can be obtained by using a “double stator” motor. In this configuration both stators can be powered together. With this concept, the number of converters is halved compared to the first mentioned solution. This saves electronic components and thus reduces the effort. All results referred to in this article are obtained by simulation, or measured on a prototype. [ABSTRACT FROM AUTHOR]

An algorithmic redundancy method is proposed in the automatic control and monitoring system of a turbojet bypass engine, based on the use of the Kalman filter and Jazwinski filter as optimal observers consistent with the mathematical model of the automatic control and monitoring system of a turbojet bypass engine. The paper provides the results of simulation of the algorithmic redundancy method employed for the measuring channel within the automatic control and monitoring system of a turbojet bypass engine based on the data from the PS-90A engine flight tests on the Tu-214 aircraft at the steady-state and transient modes. [ABSTRACT FROM AUTHOR]

This article proposes a thermally enhanced reliability modeling framework which works from the mission profile of an electrified aviation propulsion system, incorporating known fault-tolerant power electronics, motor drives, control, and their pre and postfault behaviors. The reliability framework is presented in a hierarchical fashion. Multiphysics modeling is used, incorporating electromechanical states, power losses, and thermal behaviors. The approach includes the device thermal stress in healthy and postfault operating states in the failure rate calculations. Markov chain models are then used with the calculated failure rates to form system level reliability models. A case study of an electric vertical takeoff and landing urban aerial vehicle (eVTOL UAV) walks through the proposed method, modeling multiple versions of the propulsion system, with various levels of fault tolerance and redundancy. The proposed reliability modeling framework captures the operating temperatures and thermal swings seen by the components due to the flight mission, enhancing the failure rate calculation. Further, since the postfault operating mode of the fault tolerant system causes higher component currents and temperatures, different component failure rates are calculated for postfault operation. Finally, the Markov chain modeling allows for a reliability comparison between various UAV propulsion systems, including the effect of combining fault tolerance at the subsystem level, with redundancy at the system level. [ABSTRACT FROM AUTHOR]

Nowadays, high-performance microprocessors are demanded in many fields, including those with high-reliability requirements. Commercial microprocessors present a good tradeoff between cost, size, and performance, albeit they must be adapted to satisfy the reliability requirements when they are used in harsh environments. This work presents a high-end multiprocessor hardened with macrosynchronized lockstep and additional protections. A commercial dual-core Advanced RISC Machine (ARM) cortex A9 has been used as a case study and a complete hardened system has been developed. Evaluation of the proposed hardened system has been accomplished with exhaustive fault injection campaigns and proton irradiation. The hardening approach has been accomplished for both baremetal applications and operating system (OS)-based. The hardened system has demonstrated high reliability in all performed experiments with error coverage up to 99.3% in the irradiation experiments. Experimental irradiation results demonstrate a cross-sectional reduction of two orders of magnitude. [ABSTRACT FROM AUTHOR]

In recent years, the positioning applications of Internet-of-Things (IoT) based systems have grown increasingly popular, and are found to be useful in tracking the daily activities of children, the elderly and vehicle tracking. It can be argued that the data obtained from GPS based systems may contain error, hence taking these factors into account, the proposed method for this study is based on the application of IoT-based positioning and the replacement of using IoT instead of GPS. This cannot, however, be a reason for not using the GPS, and in order to enhance the reliability, a parallel combination of the modern system and traditional methods simultaneously can be applied. Although GPS signals can only be accessed in open spaces, GPS devices are error-prone primarily when the receiver is located in an urban-canyons area, due to congestion and the possible interference. The outcome presents a redundancy-based model for improving the fault tolerance of IoT-based positioning systems. The simulation results show a 22.5% improvement in the fault tolerance of the IoT-based positioning system after applying the proposed validation mechanism, and a 77.4% improvement in this tolerance after applying for a more expensive module redundancy.

This article presents novel control strategies for a seven-level (7L) T-type active neutral-point-clamped (T-ANPC) converter based on the level-shifted pulse width modulation (LS-PWM) technique. Compared with classical 7L topologies, such as NPC, flying capacitor converter, and cascaded H-bridge converter, the 7L T-ANPC converter can reduce the device requirements while reserving the advantages of high redundancy and low conduction losses. Furthermore, the internal switching state redundancy provides freedom to balance the flying capacitor (FC) voltage and realize the fault-tolerant operation flexibly. The control strategy with modified LS-PWM technique is developed for the T-ANPC to obtain desired outputs under normal and switch open fault modes. The proposed control strategy considers the complete balancing of dc-link neutral-point voltage and FC voltages. The feasibility of the proposed 7L T-ANPC and control strategy is evaluated by simulations and experimental tests under steady-state and several typical transient operating conditions. [ABSTRACT FROM AUTHOR]

Artificial Intelligence of Things (AIoT) processors fabricated with newer technology nodes suffer rising soft errors due to the shrinking transistor sizes and lower power supply. Soft errors on the AIoT processors particularly the deep learning accelerators (DLAs) with massive computing may cause substantial computing errors. These computing errors are difficult to be captured by the conventional training on general-purposed processors such as CPUs and GPUs in a server. Applying the offline trained neural network models to the edge accelerators with errors directly may lead to considerable prediction accuracy loss. To address the problem, we propose a remote retraining framework (R2F) for remote AIoT processors with computing errors. It takes the remote AIoT processor with soft errors in the training loop such that the on-site computing errors can be learned with the application data on the server and the retrained models can be resilient to the soft errors. Meanwhile, we propose an optimized partial triple modular redundancy (TMR) strategy to enhance the retraining. According to our experiments, R2F enables elastic design tradeoffs between the model accuracy and the performance penalty. The top-5 model accuracy can be improved by 1.93%–13.73% with 0%–200% performance penalty at high fault error rate. In addition, we notice that the retraining requires massive data transmission and even dominates the training time and propose a sparse increment compression approach for the data transmission optimization, which reduces the retraining time by 38%–88% on average with negligible accuracy loss over straightforward remote retraining. [ABSTRACT FROM AUTHOR]

In this article, an adaptive fault-tolerant control scheme is proposed for nonlinear systems with actuator redundancy. To simultaneously consider multiple types of actuator faults and enable the use of an ideal system with nonlinear dynamics, the $\mathcal {L}_1$ adaptive control scheme for nonlinear time-varying reference systems is extended to systems with redundant inputs and an input gain uncertainty. The time-varying state-dependent additive uncertainty and the effectiveness of each input are selected as the adaptive parameters. A fixed, predictable control allocation is achieved through a feedback loop within the control block. The conditions for the performance bounds on the system relative to the ideal system are derived. It is shown that the performance bounds can be arbitrarily improved by increasing the adaptation rate and the feedback gain. The proposed adaptive control scheme is applied to the fault-tolerant control of an aircraft using a backstepping controller as a baseline controller, and numerical simulations are conducted to demonstrate the performance of the proposed controller for various fault scenarios. Monte Carlo simulations are conducted to verify the robustness property of the proposed controller. [ABSTRACT FROM AUTHOR]

When designing and manufacturing industrial computer systems, many different issues must be considered. The most important of these are the temporal characteristics and real-time operation. Another factor is the distribution of the system, usually over a wide area, operation in harsh environments, and, finally, the system’s dependability. When addressing the last issue, redundancy is commonly employed. This can be applied in many ways, e.g., by providing redundant communication links (buses and communication modules) and redundant sensors, input/output modules. This article considers systems that have computing unit redundancy, for which programmable logic controllers (PLCs) are often used. On the one hand, systems of this kind should be reliable and capable of real-time operations. On the other hand, they should be economically attractive. There are many solutions available on the market for the implementation of systems with redundancy. However, they are always rather expensive. Of course, the price is for a robust solution with dedicated hardware and many built-in features that are crucial in highly reliable systems, such as autodiagnostics. Nevertheless, such powerful products are not always required. This article presents an example of a cost-effective implementation of an industrial controller with hot-standby redundancy using regular devices and an Ethernet communication interface for the needs of synchronization of the computing units. For this purpose, EtherCAT and real-time Ethernet protocols were used. Note to Practitioners—This article is motivated by the problem of high cost of application of systems with computing units redundancy based on dedicated components, such as the latest S7-1500R/H Redundant System by Siemens or PACSystems Profinet System Redundancy by Emerson (former GE IP). The above solutions are powerful and sophisticated. However, sometimes, simpler solutions would suffice. This article shows how a system with computing unit redundancy could be built in a cost-effective way and, at the same time, provide all the basic features expected from systems with redundancy, i.e., fault detection, automatic switchover, and synchronization. All this is done with a common embedded programmable device and an open Ethernet-based communication network. [ABSTRACT FROM AUTHOR]

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The multiprocessor system on chips (MPSoCs) are considered today the core of most modern systems. Most of the applications of these heterogeneous MPSoCs include critical systems and hence terms of fault tolerance and reliability have become essential. Task replication is a technique to carry out fault tolerance and can help for reducing the schedule length by increasing locality. It introduces an upper and lower bound for the makespan of each schedule while each task is replicated more than once. If a fault occurs during execution, the expected makespan will be some value between the upper bound and the lower bound based on when and where the fault has occurred. In this research a new performance parameter namely the weighted average makespan is introduced. It is calculated as the average of the lower and upper bounds of makespan using the probability of occurrence of each. Two scheduling algorithms are presented for fault tolerant scheduling based on directed acyclic graphs. These algorithms are the list scheduling algorithm and the optimizing of the weighted average makespan based on simulated annealing method. The simulation results show that the techniques can improve the schedule length and increase the system reliability without compromising the performance. [ABSTRACT FROM AUTHOR]

Single event transients (SETs) have become increasingly problematic for modern CMOS circuits due to the continuous scaling of feature sizes and higher operating frequencies. Especially when involving safety-critical or radiation-exposed applications, the circuits must be designed using hardening techniques. In this brief, we present a new radiation-hardened-by-design full-adder cell on 45-nm technology. The proposed design is hardened against transient errors by selective duplication of sensitive transistors based on a comprehensive radiation-sensitivity analysis. Experimental results show a 62% reduction in the SET sensitivity of the proposed design with respect to the unhardened one. Moreover, the proposed hardening technique leads to improvement in performance and power overhead and zero area overhead with respect to the state-of-the-art techniques applied to the unhardened full-adder cell. [ABSTRACT FROM AUTHOR]

Triple modular redundancy (TMR) is a single-event upset (SEU)-mitigation technique that uses three circuit copies to mask a failure in any one copy. It improves the soft error reliability of designs implemented on SRAM-based field-programmable gate arrays (FPGAs) by masking the effects of upsets in the configuration memory. Although TMR is most effective when applied to an entire FPGA design, a reduction in the sensitive cross section of an FPGA design can be obtained by applying TMR selectively. This article explores several approaches for selecting components to triplicate. The benefit is a reduction in the neutron cross section for any output error as a percentage compared to that of a non-triplicated design. The cost is the percentage of components triplicated. The goal is to maximize the benefit–cost ratio. Twenty-five different selections are tested on a benchmark design. Some selections increase the cross section; others decrease the cross section significantly. [ABSTRACT FROM AUTHOR]

Soft processors are often used within field-programmable gate array (FPGA) designs in radiation hazardous environments. These systems are susceptible to single-event upsets (SEUs) that can corrupt both the hardware configuration and software implementation. Mitigation of these SEUs can be accomplished by applying triple modular redundancy (TMR) techniques to the processor. This article presents fault injection and neutron radiation results of a Linux-capable TMR VexRiscv processor. The TMR processor achieved a $10\times $ improvement in SEU-induced mean fluence to failure with a cost of $4\times $ resource utilization. To further understand the TMR system failures, additional post-radiation fault injection was performed with targets generated from the radiation data. This analysis showed that not all the failures were due to single-bit upsets, but potentially caused by multibit upsets, nontriplicated IO, and unmonitored nonconfiguration RAM (CRAM) SEUs. [ABSTRACT FROM AUTHOR]

Destructive single-event effects (SEEs) pose serious challenges for the reliable use of commercial off-the-shelf (COTS) devices in space systems. We modeled a simplified, redundant system to determine single-event latchup (SEL) rates that would likely compromise system reliability, resilience, and capabilities. We then assembled a representative data set of COTS Complementary Metal Oxide Semiconductor (CMOS) parts susceptible to SELs. After investigations of these parts revealed no compact distributions or other relationships useful for $a$ priori estimation of SEL rates and showed minimal correlation between Weibull fit parameters for the cross section versus linear energy transfer (LET) data, we used nonparametric statistical techniques to generate quantile plots that can be used to bound part SEL rates for a given confidence. We used these distributions to assess the threat posed to redundant systems by destructive SEEs. [ABSTRACT FROM AUTHOR]

For many Ethernet-based real-time systems, such as those from automotive, avionics, and industry automation domains, fault tolerance is emerged as an essential requirement for enabling fail-safe or fail-operational behavior. Consequently, the IEEE 802.1CB-2017 standard was published. It is currently the only available time-sensitive networking group standard offering protection against transmission errors. It tackles these faults by preventively replicating the frames and transmitting redundant copies via different paths to the destination. However, in contrast to its obvious advantages, the standard contains some pitfalls: most notably, it lacks protection mechanisms against inadequate configurations, which can not only invalidate the intended increase in reliability but even actively jeopardize the safety of the network. Due to the lack of alternative mechanisms, it is crucial to fully understand the fundamental properties of the standard and its implications on the safety aspects of the network traffic. In this letter, we identify critical aspects and limitations of the standard. We demonstrate the risks of inadequate configurations, discuss their ramifications. Finally, we provide an intuition and initial steps toward deriving the formal worst-case timing analysis of the standard, which is a key requirement for its safe and efficient implementation in the aforementioned real-time domains. [ABSTRACT FROM AUTHOR]

Electronic systems' growth causes complexity and increases the risk of failure. Fault tolerance structures are one of the useful ideas for resolving this problem. In this paper, a fault tolerant approach to digital electronic modules is introduced, using hardware redundancy to make those modules fault tolerant. The proposed structure of hardware redundancy has a voter unit that can mask and detect faults at the same time. Such a voter unit is achieved by using both majority voter units and minority voter units in its structure. The proposed voter unit has a three‐layer structure. One minority voter, three majority voters, and another minority voter are respectively producing these three layers of the proposed voter unit. These layers can mask and correct fault and detect the faulty module by producing a unique fault detecting code simultaneously. The code works properly as long as the majority of the modules work properly. Then, the result of the voter unit (the code) is transmitted to a relevant switching unit in order to switch the faulty module with a spare module. A redundant system based on the proposed redundancy structure with M spare modules can switch M faulty modules and tolerate (M + 1) faults. [ABSTRACT FROM AUTHOR]

This article evaluates the RISC-V Rocket processor embedded in a Commercial Off-The-Shelf (COTS) SRAM-based field-programmable gate array (FPGA) under heavy-ions-induced faults and emulation fault injection. We also analyze the efficiency of using mitigation techniques based on hardware redundancy and scrubbing. Results demonstrated an improvement of 3× in the cross section when scrubbing and coarse grain triple modular redundancy are used. The Rocket processor presented analogous sensitivity to radiation effects as the state-of-the-art soft processors. Due to the complexity of the system-on-chip, not only the Rocket core but also its peripherals should be protected with proper solutions. Such solutions should address the specific vulnerabilities of each component to improve the overall system reliability while maintaining the trade-off with performance. [ABSTRACT FROM AUTHOR]

Modular multilevel converters (MMCs) are frequently featured to their modular structure, which results in fault-tolerant operation and easy redundancy realization. Nevertheless, in order to reach a given redundancy factor, more cells must be included in the converter, which directly affects the costs. This paper discusses the inherent redundancy of a modular multilevel converter (MMC) based static synchronous compensator (STATCOM) operating in the overmodulation region. Analytical expressions for the limits of the converter linear region were developed in order to define the minimum required dc-link voltage. Moreover, sensitivity analyses were implemented in order to show the effects of grid voltage variations, different output impedances, power factor and injected currents. The results indicated that the operation in overmodulation region has significant inherent redundancy. For a MMC based STATCOM with 26 cells, the converter can ride through 4 failures per arm without significantly increasing the output THD or reducing the injected current into the grid. [ABSTRACT FROM AUTHOR]

The analysis of the effect of radiation exposure on integrated circuits is carried out. The methods of constructing passively fault tolerant irradiated microcircuits are considered. A review of a method for indirectly measuring the fault tolerance of such microcircuits built using various constant element-by-element redundancy and without redundancy is given. [ABSTRACT FROM AUTHOR]

The demand for highly-available systems is continuously increasing. Fault-tolerant systems which are composed of several redundant sub-units allow for continuous operation of such critical systems by distributing the system load across the functional units. However, these systems can fail if several redundant sub-units break down simultaneously. To address this, we propose a modeling and simulation approach to study the probability of simultaneous breakdown of redundant sub-units under different load distribution strategies. This allows for choosing the load-sharing strategy which achieves the highest availability for a certain system load profile and operational lifetime. We show that different load-sharing strategies can change the system availability and the operational and maintenance costs by almost an order of magnitude for a redundant power-supply unit of industrial controllers. [ABSTRACT FROM AUTHOR]

In the nanoelectronics era, multiple faults or failures in circuits and systems deployed in missionand safety-critical applications, such as space, aerospace, nuclear etc., are known to occur. To withstand these, higher order redundancy is suggested to be used selectively in the sensitive portions of a circuit or system. In this context, the distributed minority and majority voting based redundancy (DMMR) scheme was proposed as an alternative to the N-modular redundancy (NMR) scheme for the efficient implementation of higher order redundancy. However, the DMMR scheme is not self-healing. In this paper, we present a new self-healing redundancy (SHR) scheme that can inherently correct its internal faults or failures without any external intervention, which makes it ideal for mission/safety-critical applications. To achieve the same degree of fault tolerance, the SHR scheme requires fewer function blocks than the NMR and DMMR schemes. We present the architectures of the proposed SHR scheme, discuss the system reliability, and provide the design metrics estimated for example SHR systems alongside the corresponding NMR and DMMR systems using a 32/28-nm CMOS technology. From the perspectives of fault tolerance, self-healing capability, and optimizations in the design metrics, the SHR scheme is preferable to the NMR and DMMR schemes.