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Ferroelectric field-effect transistors (FEFETs) are an important candidate for emerging nonvolatile memory applications but suffer from a lack of physical understanding of the device operation. Previous FEFET models utilized the Preisach model of ferroelectrics and do not accurately capture the physics of the FEFET that the majority of the polarization charge is screened by trapped charge at the interfaces. We propose an empirical model for FEFETs, which also considers screening of ferroelectric polarization. The screening charge is modeled as a dissipative (leakage) current across the baseline MOS gate-stack. The proposed model is calibrated using the experimental data of p-type ZrO2 FEFETs and unravels the weak electrostatic coupling between the ferroelectric polarization and semiconductor channel charge. In addition, the model captures the memory window discrepancy between the charge–voltage characteristics and current–voltage characteristics observed in the experimental data, provides new insight into the ferroelectric device, and is well-suited for use as a compact model implementation of FEFETs. [ABSTRACT FROM AUTHOR]

To scale the ferroelectric random access memory (FeRAM) technology toward 28 nm or beyond, it is critical to develop stacked capacitor (with sufficient surface area) to allow good sense margin for the 1-transistor- 1-capacitor (1T1C) bit cell. Therefore, to enable 3-D integration in back-end-of-line (BEOL) process, it is essential to optimize the fabrication recipes in low-thermal budget (< 400 °C). In this regard, we investigated the low-temperature process for ferroelectric Hf0.5Zr0.5O2 (HZO) capacitor with the plasma-enhanced atomic layer deposition (PEALD). It was found that, with sufficient annealing time (>50 s) in low temperature (~ 350 °C), the ferroelectric properties of HZO could be fully manifested. No degradation is shown in the remnant polarization (Pr) under the optimized low-temperature process. Furthermore, the retention/endurance characteristics with different Pr states were measured to determine the minimally required write voltage. Finally, the SPICE simulation is conducted to evaluate the sense margin of the projected 28-nm 1T1C array with stacked cylindrical capacitors using the measured Pr drift behavior over time. [ABSTRACT FROM AUTHOR]