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In signal processing applications, the multipliers are essential component of arithmetic functional units in many applications, like digital signal processors, image/video processing, Machine Learning, Cryptography and Arithmetic & Logical units (ALU). In recent years, Profuse multipliers are there. In that, Vedic multiplier is one of the high-performance multiplications and it is used to signal/image processing applications. In order to ameliorate the performance of this multiplier further, by proposed a novel multiplier using hybrid compressor. The proposed hybrid compressor-based multiplier is designed and implemented in Field programmable Gate Array (FPGA—spartan 6). The synthesis result shows that the speed of proposed hybrid compressor-based multiplier gets improved as compared to Array multiplier (35.83%), Wallace tree multiplier (34.58%), Vedic Multiplier based on Carry look ahead adder (CLA) (28.49%), Vedic Multiplier based on Ripple carry adder (RCA) (20.65%), Booth Multiplication (21.65%) and Vedic Multiplication based on Han-Carlson Adder (HCA) (20.10%) and Hybrid multiplier using Carry Select Adder (CSELA) (17.81%) and Hybrid Vedic Multiplier (7.15%). [ABSTRACT FROM AUTHOR]

We report on the operation of a coherent population trapping (CPT) microcell atomic clock using a pulsed Ramsey-like interrogation. The Ramsey-CPT sequence, defined by two-step optical pulses separated by a free-evolution dark time, is produced by switching on and off the output power of a low-power vertical-cavity surface-emitting laser, through direct modulation of its driving current. High-contrast and narrow Ramsey-CPT fringes are detected without the use of any external optical modulator stage. We demonstrate closed-loop operation of the clock based on high-speed digital signal processing implemented in a field programmable gate array board. The clock's short-term fractional frequency stability is 1.3 × 10−10 τ − 1 / 2 until 2000 s. A power light-shift coefficient of 8 × 10−11/μW, in relative value, is obtained for a dark time of 150 μs. This value is about ten times lower than in the continuous regime. These results show the feasibility of fully integrated atomic clocks based on Ramsey spectroscopy, which could provide enhanced long-term stability. [ABSTRACT FROM AUTHOR]

This paper proposes field programmable gate array (FPGA) realization of fuzzy PI controller for typical industrial process called stirred tank heater system. Due to the complex nature of fuzzy controller families, its implementation on digital signal processors (DSPs) result computational time delay which, in other words, makes the processing speed slower. To address the limitations of DSP implementation, an alternative digital hardware programmable device called FPGAs are being largely used for digital implementation of algorithms with higher computational speed and accuracy. The proposed work is inspired by this quality of FPGAs and aims to take advantage of reliable performance of fuzzy PI controllers with its complexity and having no considerable impact on processing speed. Here, fast and novel design approach for rapid prototyping of fuzzy PI controller for stirred tank heater is presented thoroughly. Xilinx system generator SIMULINK add on from VIVADO is used to generate very high-speed integrated circuit hardware description language (VHDL) directly from MATLAB. The developed controller for stirred tank system is verified in fixed point arithmetic using Xilinx Simulink blocks. The VHDL code is then generated, synthesized, implemented, and made ready for physical implementation on Kintex-7 evaluation board. [ABSTRACT FROM AUTHOR]

Square-root unscented Kalman filter (SRUKF) is a widely used state estimator for several state of-the-art, highly nonlinear, and critical applications. It improves the stability and numerical accuracy of the system compared to the non-square root formulation, the unscented Kalman filter (UKF). At the same time, SRUKF is less computationally intensive compared to UKF, making it suitable for portable and battery-powered applications. This paper proposes a low-complexity and power-efficient architecture design methodology for SRUKF presented with a use case of the simultaneous localization and mapping (SLAM) problem. Implementation results show that the proposed SRUKF methodology is highly stable and achieves higher accuracy than the extensively used extended Kalman filter and UKF when developed for highly critical nonlinear applications such as SLAM. The design is synthesized and implemented on resource constraint Zynq-7000 XC7Z020 FPGA-based Zedboard development kit and compared with the state-of-the-art Kalman filter-based FPGA designs. Synthesis results show that the architecture is highly stable and has significant computation savings in DSP cores and clock cycles. The power consumption was reduced by 64 % compared to the state-of-the-art UKF design methodology. ASIC design was synthesized using UMC 90-nm technology, and the results for on-chip area and power consumption results have been discussed. [ABSTRACT FROM AUTHOR]

In this study, an FPGA(Field Programmable Gate Array)-based borehole strain measurement system was designed that makes extensive use of digital signal processing operations to replace analog circuits. Through the formidable operational capability of FPGA, the sampled data were filtered and denoised to improve the signal-to-noise ratios. Then, with the goal of not reducing observational accuracy, the signal amplification circuit was removed, the excitation voltage was reduced, and the dynamic range of the primary adjustments was expanded to 130 dB. The system's online compilation function made it more flexible to changes in measurement parameters, allowing it to adapt to various needs. In addition, the efficiency of the equipment use was enhanced. The actual observational results showed that this study's FPGA-based borehole strain measurement system had a voltage resolution higher than 1 μV. Clear solid tides were successfully recorded in low-frequency bands, and seismic wave strain was accurately recorded in high-frequency bands. The arrival times and seismic phases of the seismic waves S and P were clearly recorded, which met the requirements for geophysical field deformation observations. Therefore, the system proposed in this study is of major significance for future analyses of geophysical and crust deformation observations. [ABSTRACT FROM AUTHOR]

Wideband beamforming and interference cancellation for phased array antennas requires advances in signal processing algorithms, software, and specialized hardware platforms. A high-throughput array receiver has been developed that enables communication in radio frequency interference-rich environments with field programmable gate array (FPGA)-based frequency channelization and packetization. In this study, a real-time interference mitigation algorithm was implemented on graphics processing units (GPUs) contained in the data pipeline. The key contribution is a hardware and software pipeline for subchannelized wideband array signal processing with 150 MHz instantaneous bandwidth and interference cancellation with a heterogeneous, distributed, and scaleable digital signal processing (DSP) architecture that achieves 30 dB interferer cancellation null depth in real time with a moving interference source. [ABSTRACT FROM AUTHOR]

The performance of an active-quenching single-photon avalanche diode (SPAD) array that is based on the tri-state gates of a field programmable gate array (FPGA) is presented. The array is implemented by stacking a bare 4 × 4 N-on-P SPAD array on a bare FPGA die, and the electrodes of the SPAD pixels and the I/O ports of the FPGA are connected through wire bonding within the same package. The active quenching action on each SPAD pixel is performed by using the properties of the tri-state gates of the FPGA. Digital signal processing, such as pulse counters, data encoders, and command interactions, is also performed by using the same FPGA. The breakdown voltage of the SPAD pixels, with an active area of 60 μm × 60 μm, is 47.2–48.0 V. When the device is reverse biased at a voltage of ~50.4 V, a response delay of ~50 ns, a dead time of 157 ns, a dark count rate of 2.44 kHz, and an afterpulsing probability of 6.9% are obtained. Its peak photon detection probability (PDP) reaches 17.0% at a peak wavelength of 760 nm and remains above 10% at 900 nm. This hybrid integrated SPAD array is reconfigurable and cost effective. [ABSTRACT FROM AUTHOR]

This paper presents a new recursive trigonometric (RT) technique for Field-Programmable Gate Array (FPGA) design implementation. The traditional implementation of trigonometric functions on FPGAs requires a significant amount of data storage space to store numerous reference values in the lookup tables. Although the coordinate rotation digital computer (CORDIC) can reduce the required FPGA storage space, their implementation process can be very complex and time-consuming. The proposed RT technique aims to provide a new approach for generating trigonometric functions to improve communication accuracy and reduce response time in the FPGA. This new RT technique is based on the trigonometric transformation; the output is calculated directly from the input values, so its accuracy depends only on the accuracy of the inputs. The RT technique can prevent complex iterative calculations and reduce the computational errors caused by the scale factor K in the CORDIC. Its effectiveness in generating highly accurate cosine waveform is verified by simulation tests undertaken on an FPGA. [ABSTRACT FROM AUTHOR]

Compared with off-line digital signal processing (DSP) verification, achieving the expected performance and hardware efficiency in application specific integrated circuit (ASIC) is more critical for DSP to reduce power consumption and cost. The performance of traditional frequency offset compensation algorithms based on feedforward structure is strongly dependent on the accuracy of frequency offset estimation. Therefore, frequency offset calculation and loop filtering implemented in ASIC or field programmable gate array (FPGA) usually choose high word-width fixed-point or floating-point operations, which increase the consumption of logical resources and reduce the clock frequency that hardware logic can achieve. This work proposes a frequency offset compensation scheme based on polar coordinate processing and feedback structure, and a pre-decision-based angle differential estimator is used to estimate the residual frequency offset. In the proposed feedback structure, the frequency offset estimator is realized by a simple accumulator, and the input of the accumulator is the residual frequency offset or its scaling, which will reduce the requirement for the accuracy of the residual frequency offset estimator. The offline verification results show that the performance of the proposed algorithm is close to that of the traditional algorithm, but the proposed algorithm has lower logic resource consumption and higher clock frequency in hardware implementation based on FPGA. The performance of the proposed method is evaluated in real-time through 10-Gbps data rate polarization-multiplexed quadrature phase shift keying modulation after 20-km standard single-mode fiber transmission. Compared with offline processing in MATLAB®, no hardware implementation penalty is observed. [ABSTRACT FROM AUTHOR]

In radiation detector signal processing, usually, the charge-sensitive preamplifier converts the small charge signal coming from the semiconductor-based detector into voltage form and then the signal is further amplified to measure the energy of the incoming radiation. The voltage pulse from a charge-sensitive preamplifier (CSPA) is amplified using a shaping amplifier which reduces the signal bandwidth. To achieve better energy resolution, precise measurement of the peak amplitude of shaping amplifier output is required. The signal processing methods are available in which the signal from the charge-sensitive preamplifier can be directly digitized using high-speed Analog to Digital Converters (ADC), and then further signal processing such as gain and shaping is carried out inside the Field Programmable Gate Arrays (FPGA). For multiple detector systems, digital signal processing methods are quite difficult to implement in Field Programmable Gate Arrays (FPGA). In this context, The development of an alternative technique is initiated that uses a charge-sensitive preamplifier, shaping amplifier, low sampling analog-to-digital converter, and FPGA, where LaGrange's interpolation technique is implemented in FPGA to precisely measure the peak of the analog pulse. In this paper, the comparison of the proposed method with other pulse amplitude measurement techniques is discussed. Results show that the implemented technique gives similar energy resolution compared to digital pulse processing and standard peak detector-based techniques. [ABSTRACT FROM AUTHOR]

The use of floating-point units (FPU) in digital signal processing has increased due to the range and the high precision numbers that can be represented. These units are required in image processing, digital filters with infinite impulse response (IIR), finite impulse response (FIR), and digital controllers, to obtain accurate results and avoid unstable responses, however, to implement them, some processors have built-in units, this implies a technological dependency of the manufacturers when prototypes are developed. To avoid such dependency, this article presents the design of modules for the most used operations in digital signal processing: multiplication and addition/subtraction. To be able to implement these operations in any Field Programmable Gate Array (FPGA), the steps and considerations to be aware of are presented, such as exceptions, rounding, and normalization of operands. Results are verified using the MODELSIM® test bench and the error rate was determined using MATLAB®. [ABSTRACT FROM AUTHOR]

In order to improve the real-time performance of a phase-sensitive optical-time-domain reflectometer (Φ-OTDR), a fully digital phase processing system is demonstrated. Using digital down-conversion and field programmable gate array (FPGA) hardware calculation, the phase of the Rayleigh scattering light can be demodulated in real-time. Benefiting from the pipeline calculation in the FPGA, the real-time performance of this system is not affected by the interrogation rate and fiber sensing distance. Experiments show that this real-time detection system has the same vibration detection performance as an offline data process and has good stability. The dynamic strain sensing with a sensing distance of 50 km, an interrogation rate of 1 kHz, and a spatial sampling interval of 1 m is experimentally demonstrated. The obtained results indicate that the fully digital signal processing system can ensure the real-time detection of Φ-OTDR under the condition of long distance and high resolution. [ABSTRACT FROM AUTHOR]

The tracking of radiofrequency signals emission source that use directive antennas constitutes a trend in the modern telecommunication systems. The present investigation is based in the application of digital signal processing techniques in FPGA to estimate the angular position of the signal emission source using monopulse. The paper shows design and implementation of processing blocks to determinate source direction from sum and difference resulting channels of the antenna. The system is done by multidomain simulation platform Simulink and exported to hardware description language for implementation in FPGA (Field Programmable Gate Array). In the obtaining of error curve are used polynomial approximation models. The developed system is verified through eight elements antennas array with digital beamforming. [ABSTRACT FROM AUTHOR]

In this article, we present a hardware architecture optimized for sparse and dense matrix processing in TensorFlow Lite and compatible with embedded-heterogeneous devices that integrate central processing unit and field-programmable gate array (FPGA) resources. The fused architecture for dense and sparse matrices design offers multiple configuration options that tradeoff parallelism and complexity, and uses a dataflow model to create four stages that read, compute, scale, and write results. All stages are designed to support TensorFlow Lite operations including asymmetric quantized activations, column-major matrix write, per-filter/per-axis bias values, and current scaling specifications. The configurable accelerator is integrated with the TensorFlow Lite inference engine running on the ARMv8 processor. We compare performance/power/energy with the state-of-the-art RUY software multiplication library showing up to 18× acceleration and 48× in dense and sparse modes, respectively. The sparse mode benefits from structural pruning to fully utilize the digital signal processing blocks present in the FPGA device. [ABSTRACT FROM AUTHOR]

The Xilinx ZCU111 Radio Frequency System on Chip (RFSoC) is a promising solution for reading out large arrays of microwave kinetic inductance detectors (MKIDs). The board boasts eight on-chip 12-bit / 4.096 giga samples-per-second (GSPS) analogue-to-digital converters (ADCs) and eight 14-bit / 6.554 GSPS digital-to-analogue converters (DACs), as well as field programmable gate array (FPGA) resources of 930,000 logic cells and 4,272 digital signal processing (DSP) slices. While this is sufficient data converter bandwidth for the readout of 8,000 MKIDs, with a 2 MHz channel-spacing and a 1 MHz sampling rate (per channel), additional FPGA resources are required to perform the DSP needed to process this large number of MKIDs, due to a mismatch between the data converter bandwidth relative to the FPGA resources of the ZCU111. A solution to this problem is the new Xilinx RFSoC 2x2 board. This board costs only one fifth of the ZCU111 while still providing the same logic resources, albeit with only a quarter of the data converter resources. Thus, using multiple RFSoC 2x2 boards would provide a better balance between FPGA resources and data converters, allowing the full utilization of the RF bandwidth provided by the data converters, while also lowering the cost per pixel value of the readout system; from approximately €2.50 per pixel with the ZCU111 to €1 per pixel with the 2x2. [ABSTRACT FROM AUTHOR]

Field-programmable gate array (FPGA) accelerators offer performance and efficiency gains by narrowing the scope of acceleration to one algorithmic domain. However, real-life applications are often not limited to a single domain, which naturally makes Cross-Domain Multi-Acceleration a crucial next step. The challenge is, existing FPGA accelerators are built upon their specific vertically specialized stacks, which prevents utilizing multiple accelerators from different domains. To that end, we propose a pair of dual abstractions, called Yin-Yang, which work in tandem and enable programmers to develop cross-domain applications using multiple accelerators on a FPGA. The Yin abstraction enables cross-domain algorithmic specification, while the Yang abstraction captures the accelerator capabilities. We also developed a dataflow virtual machine, dubbed Accelerator-Level Virtual Machine (XLVM), which transparently maps domain functions (Yin) to best-fit accelerator capabilities (Yang). With six real-world cross-domain applications, our evaluations show that Yin-Yang unlocks 29.4× speedup, while the best single-domain acceleration achieves 12.0×. [ABSTRACT FROM AUTHOR]

Long Short-Term Memory Networks (LSTMs) are pivotal in on-device time series analysis for embedded systems, particularly for managing sensor data streams. Yet, their deployment on resource-constrained embedded devices presents notable challenges. In response, we introduce a novel parameterized architecture for LSTM accelerators designed explicitly for embedded Field-Programmable Gate Arrays (FPGAs). Our approach involves strategic design choices, such as employing computationally efficient activation functions and optimizing clock frequency with a pipelined Arithmetic Logic Unit (ALU). These decisions drive our architecture towards enhanced energy efficiency while maintaining adaptability across diverse application scenarios. A key feature of our architecture is its configurable parameters, which allow for tailored optimization through the optional use of Digital Signal Processor Slices for ALUs and the selective implementation of activation functions. Our empirical evaluations conducted on the Spartan-7 XC7S15 FPGA demonstrate the robustness of our methodology, achieving a 2.33 × improvement in energy efficiency over previous solutions. Furthermore, our study examines the correlation between memory resource types and energy efficiency across various LSTM model sizes. Impressively, even with a 9 × increase in the hidden size of the LSTM cell, our accelerator maintains an energy efficiency of 10.03 GOP/s/W, with only a minor decrease of 14.65%. However, it is critical to note that our current design is not yet optimized for larger FPGA models such as the Spartan-7 XC7S25 and XC7S50. For these models, timing constraints, rather than resource limitations, pose challenges to scaling, highlighting a potential area for future optimization. [ABSTRACT FROM AUTHOR]

Homomorphic encryption is an important technology for protecting data privacy, and the performance of modular multiplication directly affects the efficiency of homomorphic encryption. Currently, there are numerous FPGA-based acceleration techniques targeting modular multiplication. However, many of these implementations require substantial hardware resources or suffer from resource imbalance. This leads to a lower throughput. Therefore, we present a novel FPGA-based implementation of Montgomery Modular Multiplication aimed at addressing these challenges. Our design employs a suitable radix bit width and word size based on the digital signal processing (DSP) bit width rather than the conventional binary powers of two. We aim to instantiate more modular multipliers using limited resources while minimizing latency. We also introduce a novel DSP cascade structure, called parallel grouping cascade DSP, which reduces the number of clock cycles of internal multipliers. To balance the ratio of lookup table (LUT) and DSP usage, we also use multipliers implemented in the LUT to replace some DSPs. Our results, implemented on Xilinx Virtex-7 field-programmable gate array (FPGA), demonstrate more than 27% improvement in throughput on 1024-bit modular multiplication and more than 70% improvement on 2048-bit compared to the best previous state-of-the-art references. [ABSTRACT FROM AUTHOR]

Cavity BPMs are crucial for achieving submicron beam alignment in X-ray Free-Electron Lasers (XFEL), particularly in undulator sections. These monitors typically generate RF signals in the S, C, or X band regions. Due to the limitations of analog-to-digital converter's (ADC) bandwidth and sampling rates, and digital signal processing capabilities, heterodyne and homodyne receivers are often employed to down-convert the RF signal to an intermediate frequency (IF) or baseband (Zero IF) respectively before digital sampling. The digitized signal is then processed by Field Programmable Gate Array (FPGA) to get the beam position and phase information. An RF direct-sampling beam signal processor has been developed using ADCs with a bandwidth of 9 GHz and a sampling rate of 2.6 GSPS, and a powerful system-on-chip FPGA. In addition, a prototype RF module without complex down conversion devices has been designed for the SHINE (Shanghai High Repetition Rate XFEL and Extreme Light Facility) cavity BPM. The processor and the RF module make a novel RF direct sampling and processing cavity BPM electronics for SHINE. This is the first attempt to use direct sampling electronics in the C band cavity BPM system. The analog signal processing chain is greatly simplified compared to the down-conversion structure. The performance of this electronics has been analyzed and evaluated in laboratory. The amplitude relative error is 2.0 × 10-4, surpassing the required accuracy of 1 × 10-3 for cavity BPM systems. The phase error is 14 femtoseconds (fs), which also meets the requirements for an RF Beam Arrival Time Monitor (BAM) system. Additionally, the paper introduces the cavity BPM signal processing algorithms and their implementation in FPGA. The processor can deliver pulse-to-pulse beam position measurement above 1 MHz. The RF direct-sampling electronics represents significant advancements in cavity BPM system, large-scale application can be carried out in accelerator facilities like SHINE. [ABSTRACT FROM AUTHOR]

This work present an efficient hardware architecture of Support Vector Machine (SVM) for the classification of Hyperspectral remotely sensed data using High Level Synthesis (HLS) method. The high classification time and power consumption in traditional classification of remotely sensed data is the main motivation for this work. Therefore presented work helps to classify the remotely sensed data in real-time and to take immediate action during the natural disaster. An embedded based SVM is designed and implemented on Zynq SoC for classification of hyperspectral images. The data set of remotely sensed data are tested on different platforms and the performance is compared with existing works. Novelty in our proposed work is extend the HLS based FPGA implantation to the onboard classification system in remote sensing. The experimental results for selected data set from different class shows that our architecture on Zynq 7000 implementation generates a delay of 11.26 µs and power consumption of 1.7 Watts, which is extremely better as compared to other Field Programmable Gate Array (FPGA) implementation using Hardware description Language (HDL) and Central Processing Unit (CPU) implementation. [ABSTRACT FROM AUTHOR]

A new digital beam position and phase measurement (BPM) system was designed for the ion-Linac accelerator at the high intensity heavy ion accelerator facility. The fundamental and second harmonic signals are retrieved from the BPM electrodes to simultaneously calculate their respective beam positions and phases. All data acquisition and digital signal processing algorithm routines are performed in a field programmable gate array (FPGA). The position and phase information are obtained by using the in-phase and quadrature demodulation method. A practical and straightforward method is used to generate the second harmonic reference signal for processing the second harmonic beam signal. The reconfigurable filters are integrated into the FPGA to allow the measurement of short beam pulse length. The laboratory test results show that the achieved phase resolution is better than 0.2° and 0.03° when the input signal is −60 and −45 dBm, respectively. A position resolution better than 30 μm was achieved for an input power level of approximately −60 dBm, and it can reach 7 μm with the input power higher than −45 dBm. The entire execution time of the algorithm is accomplished within 3.4 µs, which provides a sufficient reaction time for the fast beam interlock signal to the machine protection system. The performance of this newly designed prototype BPM electronics was evaluated with the online proton beam. [ABSTRACT FROM AUTHOR]

In cryptography, elliptic curve cryptography (ECC) is considered an efficient and secure method to implement digital signature algorithms (DSAs). ECC plays an essential role in many security applications, such as transport layer security (TLS), internet protocol security (IPsec), and wireless sensor networks (WSNs). The proposed designs of ECC hardware implementation only focus on a single ECC variant and use many resources. These proposals cannot be used for resourceconstrained applications or for the devices that need to provide multiple levels of security. This work provides a multi-functional elliptic curve digital signature algorithm (ECDSA) and Edwardscurve digital signature algorithm (EdDSA) hardware implementation. The core can run multiple ECDSA/EdDSA algorithms in a single design. The design consumes fewer resources than the other single-functional design, and is not based on digital signal processors (DSP). The experiments show that the proposed core could run up to 112.2 megahertz with Virtex-7 devices while consuming only 10,259 slices in total. [ABSTRACT FROM AUTHOR]

This paper presents a monitoring system based on Global Navigation Satellite System (GNSS) reflected signals to provide real-time observations of sea conditions. Instead of a computer, the system uses a custom-built hardware platform that incorporates Radio Frequency (RF), Field Programmable Gate Array (FPGA), Digital Signal Processing (DSP), and Raspberry Pi for real-time signal processing. The suggested structure completes the navigation signal's positioning as well as the reflected signal's feature extraction. Field tests are conducted to confirm the effectiveness of the system and the retrieval algorithm described in this research. The entire system collects and analyzes signals at a coastal site in the field experiment, producing sea surface wind speed and significant wave height (SWH) that are compared to local weather station data, demonstrating the system's practicality. The system can allow the centralized monitoring of many sites, as well as field experiments and real-time early warning at sea. [ABSTRACT FROM AUTHOR]

Instruction level parallelism is employed by fully pipelined architecture in latest processors and the existing processor utilizes various strategies. The system proposed in this work is implemented by employing fully pipelined architecture FPU in field-programmable gate array (FPGA) and when compared to other strategies, the proposed architecture is considered to be an optimized architecture in terms of area, latency and throughput. There exist numerous challenges in performing division operation in Digital signal processing. As a result, it is essential to implement division operations in FPGA due to their complexity which is main module in many complex operations. The pipeline in every cycle of clock must be ready to accept the divider results and store in memory. A Virtex-5 FPGA uses Verilog code to build and implement DPFP (double precision floating point), which makes use of single precision floating point calculations. The proposed DPFP uses Radix-4 multiplier at lower level module to perform partial products and additions. The delay possesses 23 clock cycles and the output rate consists of 21 clock cycles. In other implementations such as high-pipelined, a large number of adders/subtractors are used in some of applications. The process delays, as well as output rate obtained are 25 and 9 clock cycles, respectively. It minimizes the amount of energy dissipated and offers several advantages such as lower area usage as well as lower latency. In most floating-point applications, the floating-point division is considered to have low-frequency as well as highlatency of operation. On the other hand, processor designers are being compelled to pay close attention to all aspects of floating-point computations because of the growing demand for excellent graphics and the widespread use of performance standards like SPEC marks. This work outlines the most widely known algorithms for floating-point division as well as implementation options that are available for the DSP applications. It also demonstrates how conventional applications of floating-point can help the designer in formulating decisions as well as trade-offs using a system-level analysis as a foundation. [ABSTRACT FROM AUTHOR]

The ability of an algorithm to extract power quality parameters on a low-end digital controller with constrained resources and computational capacity can promote comprehensive adoption of power quality control and monitoring infrastructure because of reduced cost and thus improve operational ability in a microgrid or distribution grid and support more in-depth integration of renewable energy. Since conventional harmonic extraction for single-phase grid mostly operate on Fourier transform, lock-in amplifier and their derivative algorithms, they demand large memory and computational power which are available with high-end application-specific processors, digital signal processors (DSPs) and field programmable gate arrays (FPGAs). In this paper, a computationally efficient harmonic extraction algorithm is proposed, which can be implemented on commercially available microcontrollers with ease, without compromising accuracy. A detailed theoretical analysis of the proposed method, along with various simulation and the experimental results are presented. Workarounds for minor implementation issues on digital controllers are discussed as well. [ABSTRACT FROM AUTHOR]

Hybrid field programmable gate array (FPGA) implementation is proposed to improve the performance of visible image watermarking systems. The visible watermarking process is implemented as pixel by pixel operation under a spatial domain or vector operation in the frequency domain. The proposed approach is mainly designed for watermarking the images taken from digital cameras of various sizes. The padding technique is used for unequal sizes of the watermark image and original host image. The architecture data path consists of eight and six stages of pipeline capable of watermarking on the pixel-based operation and vector-based operation, respectively. The dual image watermarking architecture data path consists of a 13-stage pipeline. Pipeline and parallelism mechanisms are used to improve throughput. To improve the performance in discrete cosine transform operations at the frequency domain, the shift-add technique replaces the conventional multipliers. The clock gating technique is employed to reduce the power by preventing unnecessary switching in a path. Hardware implementation of the algorithm is tested in Intel Cyclone FPGA with the device of EP4CGX22CF19C6, with which the throughput achieved is 1.27 Gbits/s with a total area utilization of 35 digital signal processing (DSP) blocks, 378 look-up tables (LUTs) and 486 registers. [ABSTRACT FROM AUTHOR]

Δ Σ analog-to-digital converters (ADCs) are largely used in sensor acquisition applications. In the last few years, standalone Δ Σ modulators have become increasingly available as off-the-shelf parts. To build a complete ADC, a standalone modulator has to be paired with some advanced elaboration unit, such as a field programmable gate array (FPGA) or a digital signal processor (DSP), which is needed for the implementation of the decimation filter. This work investigates the use of low-cost, general-purpose microcontrollers for the decimation of Δ Σ -modulated signals. The main challenge is given by the clock frequency of the modulator, which can be in the range of a few MHz . The proposed technique deals with this limitation by employing two serial peripheral interface (SPI) modules in a time-interleaved configuration. This approach allows for continuous acquisition and elaboration of relatively high-speed, digital signals. The technique has been applied to a case study, and a data conversion system has been practically realized. The performance of the proposed filter is compared to that of a digital filter, present on board a commercial microcontroller, and the results of experimental tests are provided. [ABSTRACT FROM AUTHOR]

This article proposes a simple and fast active power device open circuit fault detection and localization technique. The proposed technique applies to the family of flying capacitor multilevel converters (FCMCs), including dc/dc FCMCs, single or multi-phase H-bridge FCMCs, and cascaded H-bridge multilevel converters. The localization technique needs to sense the voltage and direction of current at the output terminals of converters to detect and localize the fault. A circuit with multiple window detectors is utilized to track the output voltage level and current direction with high bandwidth. The algorithm compares the measured and expected terminal voltage, considering the commanded switch states and the terminal current direction. Once potential fault locations are identified, healthy switches are filtered out from the set of potential faulty switches over successive switching transitions. The proposed technique is experimentally validated on a single phase H-bridge FCMC. The switch state commands and pulsewidth modulation (PWM) is handled by a DSP while the fault detection and localization algorithm is implemented on a separate field programmable gate array (FPGA). The asynchronous operation of the DSP and FPGA is discussed. [ABSTRACT FROM AUTHOR]

Recent developments in power electronics technologies have resulted in a need for fast responses and dynamic control. However, existing control schemes are still limited to the available digital signal processors (DSPs) and their associated high prices. The field-programmable gate array (FPGA) offers fast performance and high control flexibility by providing a reconfigurable computing speed. However, it has some implementation limitations in standalone systems. In this regard, this paper presents a hardware setup for a three-level hybrid active neutral point inverter (HANPC) using a FPGA and a DSP. A unique method using digital and analog modulation is designed in this study using Vivado software. The proposed method depends on receiving analog reference signals from the DSP and then performing all the required processes using the FPGA. Direct pulse width modulation is generated to control the HANPC without changing the hardware configuration of the main topology. The implemented hardware is based on a 15 kW HANPC topology that is mainly controlled by a Digilent Zybo-Z7-20 FPGA. The effectiveness of the proposed system was verified by experimental results. [ABSTRACT FROM AUTHOR]

Capacitance monitoring is one of the important issues for a modular multilevel converter (MMC) to obtain high reliability. Since pulsewidth modulation is usually implemented in the field-programmable gate array (FPGA), produced precise switching states in the FPGA cannot be directly accessed by the top digital signal processor (DSP) controller, which poses challenges to the existing capacitance monitoring methods based on precise switching states of the MMC. This article presents a submodule (SM) capacitance monitoring strategy for the MMC with a simple algorithm, where the fundamental frequency components of the SM capacitor voltage and current are extracted to estimate the SM capacitance based on reference, but not the precise switching states. The proposed scheme not only simplifies the implementation and calculation, but also avoids control limitations and heavy communication burden between the DSP and the FPGA. Besides, the proposed strategy effectively eliminates noise impact from sensors and increases accuracy. Simulation and experimental studies are implemented, and the results confirm the effectiveness of the proposed strategy. [ABSTRACT FROM AUTHOR]

The reversible computation is the process of designing the architecture with reversible logic gates (RLG) and applicable for optical computing, digital signal processing, nanotechnologies and low-power circuits. In this study, integer wavelet transform (IWT) compression technique is applied to the input image to compress the pixel value. The utilization of the IWT is used to improve the quality of the image in terms of peak signal-to-noise ratio (PSNR) and structural similarity index matrix (SSIM). In addition, different types of RLGs are used to perform the encryption and decryption of the images. A random number is generated using the Lorenz chaotic system (LCS) that contains three different stages and each stage is developed using arithmetic blocks. Here, an effective key value is generated from the input image values by connecting the LCS's output with the heterogeneous key generation (HKG) module. The inverse IWT (IIWT) technique is used to retrieve the original data during execution of decryption operation. Application specific integrated circuit and field-programmable gate array (FPGA) performances are calculated for reversible logic cryptographic design (RLCD) IWT-HKG architecture. The results showed that it has achieved better performance compared to conventional methods. Moreover, security analyses such as avalanche effect, side channel attack and session key agreement are performed for the RLCD-IWT-HKG method. The RLCD-IWT-HKG method has achieved 89 LUTs, 52 flip flops and 31 slices for the Virtex 6 FPGA device. After retrieving the decrypted images, values of PSNR and SSIM are evaluated as 39.90 dB and 0.6874, respectively. [ABSTRACT FROM AUTHOR]

High-fidelity electromagnetic transient (EMT) simulation plays a critical role in understanding the dynamic behavior and fast transients involved in operation, control, and protection of multiterminal dc (MTdc) grids. This article proposes a cost-effective high-performance real-time EMT simulation platform for large-scale cross-continental MTdc grids based on graphics processing unit (GPU). Fast dynamic transients from both ac and dc networks are captured in real time with 5 μs time step, using advanced hybrid-discretized modular multilevel converter model, frequency-dependent transmission line model, and EMT-type model of synchronous generators. The proposed simulation platform i) assembles detailed EMT models of all components within an MTdc–ac grid into a single platform. This setup provides a complete simulation solution to capture fast transient signals required for high-bandwidth controller design and protection studies without any compromise; ii) implements the first GPU-based simulation architecture and corresponding algorithms for MTdc–ac grids with real-time performance at scales of 1s; iii) is highly efficient and balances the high utilization of GPU resources and low latency required for the simulation; and iv) outperforms the existing central processing unit- or digital signal processor (DSP)/field-programmable gate array-based simulators in terms of its higher scalability on large-scale MTdc–ac grids and superior price–performance ratio on the hardware. Accuracy and performance of the proposed platform are evaluated with respect to the reference results from power system computer aided design (PSCAD)/EMTdc environment. [ABSTRACT FROM AUTHOR]

A new Mössbauer spectrometer based on a CompactRIO platform was developed. The CompactRIO is a modular industrial computer platform developed by the National Instruments. This device runs under “LabVIEW RT OS”—Linux-based real-time operating system, which has a support of the LabVIEW programming environment. The CompactRIO has an integrated field programmable gate array (FPGA), which was used for most critical functions of the developed spectrometer, such as scintillation detector signal acquisition and accumulation of Mössbauer spectra, and for driving a velocity transducer movement using a proportional–integral–derivative (PID) regulation. The velocity transducer modulates gamma rays’ energy by movement using the Doppler effect. Precision of this movement is crucial, as it defines whole spectrometer accuracy. More sophisticated algorithms (i.e., PID parameters autotuning and additional Mössbauer spectra linearization methods) have been implemented on the real-time part of the CompactRIO. The developed spectrometer demonstrates the advantages of the real-time systems such as deterministic processing of large amounts of data allowing measurement in a very high velocity resolution. [ABSTRACT FROM AUTHOR]

A complete description of a field-programmable gate array (FPGA)-based smart energy meter is presented in this article. By implementing the power quantities definitions of the IEEE 1459–2010 Standard, a novel power quality analyzer capable of performing remote monitoring of electric power systems operating under sinusoidal, nonsinusoidal, balanced, and/or unbalanced conditions was developed. In order to ensure portability, the digital signal processing algorithms implemented on the FPGA device were entirely coded in hardware description languages, and all equations of them are fully described to be applied to any digital signal processing environment. These algorithms are completely defined as functions of the grid fundamental frequency, and by adjusting the sampling frequency, the adaptability of all modules developed is ensured. Experimental results were obtained using the developed platform in a three-phase four-wire system operating under several conditions, which were defined by the presence of harmonic components imposed by nonlinear loads and supply voltages, as well as by setting bidirectional power flow in distributed generation scenarios by employing a photovoltaic system. Real-time and parallel processes are validated as well. [ABSTRACT FROM AUTHOR]

We present the development and characterization of a generic, reconfigurable, low-cost (< 350$) software-defined digital receiver system (DRS) for temporal correlation measurements in atomic spin ensembles. We demonstrate the use of the DRS as a component of a high-resolution magnetometer. Digital receiver-based fast Fourier transform spectrometers (FFTSs) are generally superior in performance in terms of signal-to-noise ratio (SNR) compared with traditional swept-frequency spectrum analyzers (SFSAs). In applications where the signals being analyzed are a very narrow band in the frequency domain, recording them at high speeds over a reduced bandwidth provides flexibility to study them for longer periods. We have built the DRS on the STEMLab 125-14 FPGA platform, and it has two different modes of operation: FFT spectrometer and real-time raw voltage recording mode. We evaluate its performance by using it in atomic spin noise spectroscopy (SNS). We demonstrate that the SNR is improved by more than one order of magnitude with the FFTS compared with that of the commercial SFSA. We also highlight that with this DRS operating in the triggered data acquisition mode, one can achieve a spin noise (SN) signal with high SNR in a recording time window as low as 100 ms. We make use of this feature to perform time-resolved high-resolution magnetometry. While the receiver was initially developed for SNS experiments, it can be easily used for other atomic, molecular, and optical (AMO) physics experiments as well. [ABSTRACT FROM AUTHOR]

The Fast Fourier Transform (FFT) is one of the most important algorithm used in digital signal processing (DSP) and digital communication applications to compute fast operations. FFT and IFFT is widely used in modulation and demodulation schemes such as Orthogonal Frequency Division Multiplexing (OFDM), TV broadcasting (DVD), Digital radio broadcasting (DVB) etc. The different FFT processor architectures are used for several applications. The Xilinx ISE tool has FFT Core, which can be directly used for several applications. FFT support four types of architectures: Radix-2 lite burst I/O, Radix-2 burst I/O, Radix-4 burst I/O and Pipelined I/O. The research article focuses on the hardware chip performance analysis of the variable length FFT processor architectures on Field Programmable Gate Array (FPGA) platform using VHDL programming in which FFT length varies from 8 point to 65,536 point. The input data stream is considered of 8-bit, 16-bit and 32-bit. The estimated hardware chip performance parameters are DSP Slices and block RAM. The timing parameter are transform cycles and frequency. It is estimated that radix-2 lite burst I/O performs better in terms of hardware resource utilisation on FPGA and pipelined hardware architecture performs better in terms of transform cycles in comparison to other FFT architectures. The decoded 1024-point FFT signal is observed in Xilinx ISE software integrated Chipscope Pro-Analyzer. The analysis predicts about the best-suited FFT hardware architecture when the designer is going to design the hardware chip on FPGA platform for several applications. [ABSTRACT FROM AUTHOR]

The High Intensity heavy ion Accelerator Facility (HIAF) and Low Energy heavy ion Accelerator Facility (LEAF) of IMP are under construction. They will comprise many superconducting devices and components, such as magnets and current leads, with the superconducting materials covering NbTi, Nb3Sn and HTS. On the other hand, most of the superconducting devices have a high energy density and complex structure, requiring a targeted and active protection. In previous quench protection systems implemented at IMP, the quench detection was implemented in software or as microcontroller-based equipment, where power supplies in superconducting circuit provided quench detection functionality as well. These systems have some disadvantages, such as limited functionalities, poor reliability and high susceptibility to interference. Therefore, a new type of quench detection system (QDS) based on programmable FPGA and Isolated analogue input front-ends was developed to overcome these challenges. It is important to note that in the test facilities, there is no ionizing radiation, the QDS does not require radiation tolerance, thus a commercial programmable FPGA product was chosen as the development platform. The QDS is currently being put into operation, and some good results have been obtained in the cold tests of MCBRDP2 (belongs to HL-LHC, NbTi magnet) and FECR (belongs to LEAF, Nb3Sn magnet). Based on these successful applications, the new QDS has proven its functionality. The recorded data and practical experience also provided relevant information for the detection algorithms and functional upgrades. [ABSTRACT FROM AUTHOR]

Fixed-point multiplication is an important operation that is frequently used in many digital signal processing (DSP) applications. The operation is computationally intense and very often the performance of multiplier determines the overall performance of DSP system. Evidently, a wide range of approaches have been proposed for efficient implementation of fixed-point multipliers on different hardware platforms. In this paper, we use Coordinate Rotation DIgital Computer (CORDIC) algorithm to perform fixed-point multiplication operation. The motivation for our approach is based on the fact that CORDIC is a hardware-efficient algorithm, wherein accuracy can be traded-off for performance. Our implementation targets field programmable gate arrays (FPGAs) and focuses on exploiting the underlying general and specialized fabric to the fullest. Performance comparisons against various traditional and recent approaches show that a substantial improvement is achievable by using CORDIC-based multipliers. We have also implemented a recently proposed convolution architecture using CORDIC-based multipliers. The results show that a proper choice of CORDIC architecture can result in an improvement of performance parameters like resource utilization, throughput and dynamic power. This, however, is achieved in lieu of a small cost in accuracy. Our analysis of an 8-stage CORDIC multiplier reports a mean absolute percentage error (MAPE) of 6.032 — a factor that reduces exponentially with increasing number of stages. [ABSTRACT FROM AUTHOR]

Improving the visibility of hazy images is desirable for robot navigation, security surveillance, and other computer vision applications. The presence of fog significantly damages the quality of the captured image, which does not only affect the reliability of the surveillance system but also produce potential danger. Therefore, developing as well as implementing a simple and efficient image de-hazing algorithm is essential. The reconfigurable computing devices like Field Programmable Gate Array and Digital Signal Processing (DSP) processors are used to implement these image processing applications. Several strategies are available for configuring these reconfigurable devices. In this paper, two approaches for hardware implementation of image de-hazing algorithm are presented. The pixel wise and gray image-based de-hazing algorithm is proposed in this paper. The key advantage of this proposed method is to estimate accurate transmission map. It eliminates the computationally complex step of refine transmission map as well as halos & artifacts in the recovered image and achieves faster execution without noticeable degradation of the quality of the de-hazed image. The proposed method is initially verified in MATLAB and compared with the existing four state-of-art methods. This algorithm is implemented on two different hardware platforms, i.e., DSP Processor (TMS320C6748) with floating pointing operations and Zynq-706 fixed-point operations. The performance comparison of hardware architectures is made with respect to Average Contrast of the Output Image, Mean Square Error, Peak Signal to Noise Ratio, Percentage of Haze Improvement and Structural Similarity Index (SSIM). The results obtained show that Zynq-706-based hardware implementation processing speed is 1.33 times faster when compared to DSP processor-based implementation for an image dimensions of 256 × 256 . [ABSTRACT FROM AUTHOR]

Multiplication is one of the most extensively used arithmetic operations in a wide range of applications. In order to provide resource-efficient and high-performance multipliers, previous works have proposed different designs of accurate and approximate multipliers—mainly for ASIC-based systems. However, the architectural differences between ASICs- and FPGA-based systems limit the effectiveness of these multipliers for FPGA-based systems. Moreover, most of these multiplier designs are valid only for unsigned numbers. To bridge this gap, we propose a novel implementation technique for designing resource-efficient and low-power accurate and approximate signed multipliers which are optimized for FPGA-based systems. Compared to Vivado's area-optimized multiplier IPs, the designs obtained using our proposed technique occupy 47 to 63 percent less area (Lookup Tables). To accelerate further research in this direction and reproduce the presented results, the RTL and behavioral models of our proposed methodology are available as an open-source library. 1. Online. [Available]: https://cfaed.tu-dresden.de/pd-downloads. [ABSTRACT FROM AUTHOR]

The new digital multichannel analyzer (DMCA) based on field programmable gate array (FPGA) technology is successfully developed, and it is used for liquid scintillation detection. The performance of this system has been evaluated. The analog signal output emanating from the photomultiplier tube (PMT) is transformed into digital signals through the utilization of an amplifier and a high-speed analog-to-digital converter (ADC). Information about the energy, timing, and pulse shape characteristics of the radiation event is contained in the digital signal. Subsequently, this digital signal is directed towards the FPGA for digital signal processing. In order to reduce the thermal and electronic noise, the dual-channels configuration and the signal coincidence function are added to DMCA for optimizing the validity of signal. The signal coincidence unit is designed within the FPGA, optimizing the synchronization of signals. The measurement data is transmitted to a computer via USB interface. The energy spectra of gamma sources, namely 22Na, 60Co, and 137Cs, as well as the alpha source 232Th, were measured utilizing the newly developed system. Notably, thermal and electronic noise interference is reduced in the coincidence measurement mode, and the coincidence energy spectra are improved compared to the singles measurement. In contrast to commercially available systems, the advantages of our design in terms of miniaturization, cost-effectiveness, and expandability are demonstrated. [ABSTRACT FROM AUTHOR]

In recent years, a variety of accelerators on FPGAs have been proposed to speed up the convolutional neural network (CNN) in many domain-specific application fields. Besides, some optimization algorithms, such as fast algorithms and network sparsity, have greatly reduced the theoretical computational workload of CNN inference. There are currently a few accelerators on FPGAs that support both the fast Winograd algorithm (WinoA) and network sparsity to minimize the amount of computation. However, on the one hand, these architectures feed data into processing elements (PEs) in units of blocks, some boundary losses caused by sparse irregularities cannot be avoided. On the other hand, these works have not discussed the design space exploration under the sparse condition. In this article, we propose a novel accelerator called WINONN. We fully discuss the challenges faced by supporting WinoA, weight sparsity, and activation sparsity simultaneously. To minimize the online encoding overhead caused by activation sparsity, an efficient encoding format called multibit mask (MBM) is proposed. To handle the irregularities of sparse data, we proposed a novel Scatter-Compute-Gather method in hardware design, combined with a freely sliding buffer to achieve fine-grained data loading to minimize the boundary waste. Finally, we combine a theoretical analysis and experimental method to explore the design space, allowing WINONN to get the best performance on a specific FPGA. Our high scalability design enables us to deploy sparse Winograd accelerators on very small embedded FPGAs, which is not supported in previous works. The experimental results on VGG16 show that we achieve the highest digital signal processing unit (DSP) efficiency and highest energy efficiency compared with the state-of-the-art sparse architectures. [ABSTRACT FROM AUTHOR]

Field programmable gate arrays (FPGAs) are attractive for a digital spectrometer due to its advantages of digital signal processing. However, how to improve the versatility of the spectrometer and increase the operating frequency of the digital shaper has gradually become a limitation that needs to be resolved in the FPGA-based spectrometer. A solution to improve the universality of the FPGA-based digital spectroscopy system is presented in this work, and the implementation of the real-time digital signal processing unit is improved to obtain a higher operating frequency, and then the optimal parameters of the digital trapezoidal shaper and the processing unit are also discussed through a series of experiments; finally, a FPGA-based digital spectrometer is developed. With the HPGe detector, the spectrometer achieves excellent energy resolution performance of 0.35% at 662 keV, 0.25% at 1173.2 keV, and 0.23% at 1332.5 keV. [ABSTRACT FROM AUTHOR]

Flow rates of fuel are a major control variable in the engines of airborne vehicles. Accuracy in flow rate measurements became a mandatory requirement for the testing and reliable operation of those engines. Flow rate measurement is also essential in food industries, automotive industries, and chemical industries. Flow rate measurement using ultrasonic transducers is an appropriate choice because of its unique properties when they are in contact with the gases and water medium, as well as larger diameter pipelines. Estimating the echo signal of the ultrasonic flowmeter is a challenging task; however, the processing tasks for real-time performance are mandatory for improving accuracy in flow rate measurements. This article reviews the improvement in the accuracy of flow rate measurements of liquids and gases incorporating the modern technological trends with the support of field programmable gate arrays, digital signal processors, other advanced processors, and deep learning approaches. The review also elaborates on the reduction of uncertainty in single path and multi-path ultrasonic flowmeters. Finally, future research prospects are put forward for developing low cost, reliable, and accurate ultrasonic flowmeters for extensive categories of industrial applications. [ABSTRACT FROM AUTHOR]

Long-horizon finite-control-set model predictive control is implemented on a field-programmable gate array (FPGA). To solve the underlying least-squares integer program, a nonrecursive sphere decoding algorithm is developed. By exploiting the problem structure, few multipliers are required, and the algorithm computes the optimal solution in a few clock cycles, thus achieving a resource-efficient implementation on the FPGA. For a prediction horizon of five steps and a three-level converter, 87 digital signal processor blocks, and an execution time of at most $\text{13.4}\;\mu \text{s}$ was required to solve the optimization problem during steady-state operation. Experimental results verify the effectiveness of the long-horizon controller. [ABSTRACT FROM AUTHOR]