Search

This paper investigates the field-programmable gate array (FPGA) implementation of a fault-tolerant space vector-hysteresis current control (SV-HCC) for three-phase grid-connected converter. The proposed control ensures continuous operation despite of an open-circuit fault in one grid current measurement circuit (caused by defected cables, lines or connectors at the output of the current measurement circuit). It is based on hardware redundancy of current measurement circuits for fault detection and isolation. The faulty measured current is identified through the computation of residuals with well-defined thresholds. Thanks to the high computation capabilities of FPGAs, the implemented fault-tolerant SV-HCC is executed with a very high sampling frequency and very low execution time. As a consequence, the defined theoretical thresholds remain available for the experimental tests. Several experimental results, carried out on FPGA-based prototyping platform, are given in order to illustrate effectiveness and reliability of the proposed fault-tolerant SV-HCC. [ABSTRACT FROM AUTHOR]

This paper deals with a hybrid fault-tolerant converter topology. It is performed through the connection of a classical three-phase three-level neutral-point-clamped (3L-NPC) converter with a fourth three-level flying capacitor (3L-FC) leg. The 3L-FC leg actively balances the 3L-NPC neutral-point voltage. For normal operation mode, this paper proposes a mathematical design of the filter needed to connect these two different topologies. Experimentally, and thanks to the already existing decoupling capacitors of the 3L-NPC converter, this filter requires the addition of only one low size inductance. When one fault of the power switch of the 3L-NPC occurs, this paper proposes a hardware reconfiguration technique based on only two fuses and one thyristor per leg allows a safe postfault operation recovery. This is achieved thanks to a simple fault-detection method and a new technique that combines fault leg isolation and corresponding phase postfault connection to the neutral point. Also, a dedicated field-programmable gate array (FPGA)-based control of the reconfigured converter is synthetized to ensure power system availability under fault operation mode. The converter fault-tolerant capabilities are addressed through simulation results and original overall experimental validations of the fault detection and isolation and the postfault operation steps, carried out on a 15-kW prototype converter. [ABSTRACT FROM AUTHOR]

This paper deals with embedded real-time (RT) simulators applied in power electronic applications and implemented in low-cost field-programmable gate arrays. Indeed, such simulators' intellectual properties (IPs) are not only intended for hardware-in-the-loop (HIL) testing but also can be advantageously embedded within digital controllers to ensure functions such as observation, estimation, diagnostic, or health monitoring. Conversely, to the HIL case, the main challenge when designing such simulators' IPs is to cope with their complexity having in mind that, in the case of embedded systems, the available hardware resources are limited due to the cost. Furthermore, this challenge is strengthened by the need of very short simulation time steps that is typically the case when simulating power converters. By this way, this paper presents the design of an embedded RT simulator of a three-phase grid-connected voltage-source rectifier, based on the associated discrete circuit modeling approach. This IP is associated with the one of a three-phase $RL$ filter, and both are implemented within the rectifier controller to estimate the grid currents. The latter is injected in the controller when a fault is detected in the current sensors. The ability of this estimator to guarantee the service continuity in case of faults has been validated through HIL tests and experiments. [ABSTRACT FROM PUBLISHER]