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The recent progress in quantum computing and space exploration led to a surge in interest in cryogenic electronics. Superconducting devices such as Josephson junction, Josephson field effect transistor, cryotron, and superconducting quantum interference device (SQUID) are traditionally used to build cryogenic logic gates. However, due to the superconducting nature, gate-voltage-based control of these devices is extremely difficult. Even more challenging is to cascade the logic gates because most of these devices require current bias for their operation. Therefore, these devices are not as convenient as the semiconducting transistors to design logic gates. Here, to overcome these challenges, we propose a ferroelectric SQUID (FeSQUID) based voltage-controlled logic gates. FeSQUID exhibits two different critical current levels for two different voltage-switchable polarization states of the ferroelectric. We utilize the polarization-dependent (hence, voltage-controllable) superconducting to resistive switching of FeSQUID to design Boolean logic gates such as Copy, NOT, AND, and OR gates. The operations of these gates are verified using a Verilog-A-based compact model of FeSQUID. Finally, to demonstrate the fanning out capability of FeSQUID-based logic family, we simulate a two-input XOR gate using FeSQUID-based NOT, AND, and OR gates. Together with the ongoing progress on FeSQUID-based non-volatile memory, our designed FeSQUID-based logic family will enable all FeSQUID-based cryogenic computer, ensuring minimum mismatch between logic and memory blocks in terms of speed, power consumption, and fabrication process. [ABSTRACT FROM AUTHOR]

This brief exploits the fusion of low-power logic and nonvolatile memory inside the emerging ferroelectric FETs (FeFETs) and proposes a new nonvolatile D flip-flop (nvDFF) through the device-circuit co-design. Compared with existing FeFET-based nvDFFs with on-demand control of backup and restore (B&R), the area overhead is lowered by half, and the routing cost is reduced with embedded backup control into the supply voltage. Circuit simulations show below 5% energy-delay overhead in the normal mode and femtojoule B&R energy. This new nvDFF promises area- and energy-efficient nonvolatile computing for power-gating and energy-harvesting applications. [ABSTRACT FROM AUTHOR]

Ferroelectric FETs (FEFETs) are emerging devices with an immense potential to replace conventional MOSFETs by virtue of their steep switching characteristics. The ferroelectric (FE) material in the gate stack of the FEFET exhibits negative capacitance resulting in voltage step-up action which entails sub-60 mV/decade subthreshold swing at room temperature. The thickness of the FE layer ( T\textsf {FE}) is an important design parameter, governing the device-circuit operation. This paper extensively analyzes the impact of T\textsf {FE} on the device-circuit characteristics in conjunction with the interactions between FE and gate/drain capacitances. While it is well known that increasing T\textsf {FE} yields higher gain albeit with the possibilities of introducing hysteresis, our analysis points to other unconventional effects emerging in circuits as T\textsf {FE} is increased. Depending on the attributes of the underlying transistor, increasing T\textsf {FE} beyond a certain value may lead to loss in saturation and/or negative differential resistance in the output characteristics. While the former effect results in the loss in gain of a logic gate, the latter may yield hysteretic voltage transfer characteristics. We also discuss the effect of T\textsf {FE} on the circuit energy–delay. Our analysis shows that for high T\textsf {FE} , the delay of the circuit may increase with an increase in supply voltage. However, for voltages <0.25 V, FEFINFETs show an immense promise yielding 25% lower energy at iso-delay. [ABSTRACT FROM PUBLISHER]

Negative capacitance FETs (NCFETs) have attracted significant interest due to their steep-switching capability at a low voltage and the associated benefits for implementing energy-efficient Boolean logic. While most existing works aim to avoid the ID – VG hysteresis in NCFETs, this paper exploits this hysteresis feature for logic-memory synergy and presents a custom-designed nonvolatile NCFET D flip-flop (DFF) that maintains its state during power outages. This paper also presents an NCFET fabricated for this purpose, showing <10 mV/decade steep hysteresisedges and high, up to seven orders inmagnitude, R\text {DS} ratio between the two polarization states. With a device-circuit codesign that takes advantage of the embedded nonvolatility and the high R\text {DS} ratio, the proposed DFF consumes negligible static current in backup and restore operations, and remains robust even with significant global and local ferroelectric material variations across a wide 0.3–0.8 V supply voltage range. Therefore, the proposed DFF achieves energy-efficient and low-latency backup and restore operations. Furthermore, it has an ultralow energy-delay overhead, below 2.1% in normal operations, and operates using the same voltage supply as the Boolean logic elements with which it connects. This promises energy-efficient nonvolatile computing in energy-harvesting and power-gating applications. [ABSTRACT FROM PUBLISHER]

Hyper-FET, an emerging device with unconventional characteristics, exhibits sub-kT/q switching and can attain higher ON current ( I \mathrm{\scriptscriptstyle ON} ) than standard FinFETs with matched OFF current ( I \mathrm{\scriptscriptstyle OFF} ). In continuation to the insights on the device level design methodology conveyed in part I [1], here we analyze the circuit implications of the unique characteristics of Hyper-FETs, such as hysteresis and abrupt switching. We provide a comprehensive discussion on the design of Hyper-FET-based circuit primitives, such as inverter, NOR and NAND gates. We emphasize on tailoring the hysteresis to avoid functional failure in logic circuits and deduce the correspondence between hysteresis observed in the device and circuit characteristics. To complement the device level constraints presented in part I, here we present additional stringencies for material parameters to aid in designing Hyper-FET-based logic gates with regenerative property and rail-to-railswing. Our analysis indicates that, at low V\sf DD (<0.3 V), properly designed Hyper-FET-based inverters can exhibit 25%–68% less energy at iso-delay (compared with FinFET-based CMOS inverters). We also provide targets for future material exploration. [ABSTRACT FROM AUTHOR]

We present a SPICE model for ferroelectric transistors (FEFETs) based on time-dependent Landau–Khalatnikov equation solved self-consistently with the transistor equations. The model also considers depolarization fields due to non-ideal contacts. We experimentally characterize FE films to calibrate our model, based on which we analyze the device and circuit implications of FEFETs. We discuss the dependence of the ON current and gate capacitance of FEFETs on the FE thickness and FE material parameters. A ring oscillator analysis shows delay reduction up to 97% at iso-energy for FEFETs compared with MOSFETs at V\mathrm{ DD}<0.4 V. FEFET-based SRAMs show 47%–68% larger read stability and 50%–57% lower access time, albeit with an increase in the write time. [ABSTRACT FROM PUBLISHER]