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DC characteristics of n-type SiGe heterojunction nanowire tunneling field-effect transistors (TFETs) adopting a core–shell structure are investigated using 3-D numerical simulation. Different mole fractions between the core and the shell regions induce strain effects along the nanowire, which modulate the energy bandgap and thus the dc performance of the devices. The SiGe core–shell TFETs with greater mole fractions in the core regions increase the drive currents greatly by both Ge content and strain effects which decrease the tunneling length and increase the band-to-band (BTB) generation rate according to Kane’s nonlocal tunneling model. In addition, tensile (compressive) strains for the shell (core) regions as well as shear strains reduce the energy bandgap according to the deformation potential theory, decreasing the subthreshold swing as well as increasing the BTB generation rate. Compared to all other Si/Ge heterojunction TFETs, the proposed SiGe core–shell TFETs are superior with high drive currents and on/off-current ratios. [ABSTRACT FROM PUBLISHER]

Process-induced variations of 10-nm node n-type FinFETs considering middle-of-line parasitics were investigated in terms of dc/ac performances using fully calibrated TCAD simulations. Variations of positive fixed oxide charge density at shallow trench isolation interface and source/drain (S/D) height influenced off-state and on-state performance variations, respectively, but slightly on RC delay variations. Fin width variations induced off-state performance and RC delay variations critically due to the fluctuation of short channel effects. But, fin height variations affected them slightly due to the preserved gate-to-channel controllability and the buffered effects by varying drain currents and gate capacitances in the same direction. Gate length, spacer length, and S/D length variations influenced dc/ac performance variations severely; 2-nm-length changes were barely acceptable to satisfy 10% RC delay margin. Thus, the process-induced variability parameters, including fin width, gate length, spacer length, and S/D length, should be controlled tightly under a few nanometers to reduce dc/ac performance variations of the FinFETs. [ABSTRACT FROM AUTHOR]

In this brief, we systematically investigated the effects of fin pitch (FP) and fin height ( H\textrm {fin} ) on parasitic resistances and capacitances to achieve the best RC delay, which is an adequate metric of the ac behavior of FinFETs, for Si bulk n/pFinFETs in system-on-a-chip applications. The RC delays were directly extracted from the fully calibrated technology computer aided design I – V/C – V simulation results and quantitatively analyzed using parasitic capacitance components, including a middle-of-the line configuration up to Metal 1. When FP increased, the . On the other hand, the RC delay mostly decreased due to greater ON-current as the H\textrm fin increased. The RC delay with different power supply voltages ( V\textrm {DD} = 0.55 and 0.75 V) was also studied to see the effect of V\textrm {DD} scaling. Finally, a selective deposition was suggested to improve the $RC$ delay about 13%. [ABSTRACT FROM PUBLISHER]

A compact scaling length model for tapered Tri-gate fin field-effect transistors (FinFETs) is presented based on a 3-D simulation and an analytic potential model. Short-channel effects (SCEs) of rectangular FinFETs can be controlled by designing the fin width, fin height, and gate length to satisfy scaling theory. Tapered FinFETs have a fin top width shorter than the fin bottom width, and they show a different dependence of subthreshold behaviors and SCEs compared to rectangular FinFETs. The proposed scaling length model for tapered FinFETs, expressed as a function of fin bottom width, fin height, and tapering angle, is presented based on the 3-D Poisson's equation and a non-Cartesian mesh. The dependence of the subthreshold behaviors of tapered FinFETs calculated with the proposed model is compared with that of rectangular FinFETs. We found that longer fin bottom widths and fin heights of tapered FinFETs can be designed by applying the proposed scaling length model for the scaling parameter. [ABSTRACT FROM AUTHOR]

In this paper, a simple but accurate model is presented to analyze source/drain (S/D) series resistance in trigate fin field-effect transistors, particularly on triangular or pentagonal rather than rectangular epitaxy. The model includes the contribution of spreading, sheet, and contact resistances. Although the spreading and sheet resistances are evaluated modifying standard models, the contact resistance is newly modeled using equivalent models of lossy transmission lines and transformations of 3-D to 2-D geometry. Compared with series resistance extracted from 3-D numerical simulations, the model shows excellent agreement, even when the S/D geometry, silicide contact resistivity, and S/D doping concentration are varied. We find that the series resistance is influenced more by contact surface area than by carrier path from the S/D extension to the silicide contact. To meet the series resistance targeted in the semiconductor roadmap, both materials and geometry will need to be optimized, i.e., lowering the silicide contact resistivity and keeping high doping concentration as well as maximizing the contact surface area, respectively. [ABSTRACT FROM PUBLISHER]

The low-frequency noise (LFN) of a p-type nanowire FET (p-NWFET) was characterized and compared with that of an n-type NWFET (n-NWFET) in terms of dominant noise source and its location in the channel region. An inverse proportional dependence of the noise level on channel diameter was observed in the p-NWFET but not in the n-NWFET. The LFN was observed to be mainly generated by Hooge mobility fluctuation in the p-NWFET. Under a switched biasing condition, p-NWFET showed no substantial LFN reduction (in contrast to the n-NWFET), indicating that the carrier number fluctuation was insignificant. This was due to the compressive stress induced by embedded SiGe with heavier transverse effective hole mobility. [ABSTRACT FROM AUTHOR]

The conventional source/drain series resistance (Rsd) extraction method is not applicable to nanowire field effect transistors (NWFETs), as NWFETs have fluctuating characteristics in Id and there is insufficient physical modeling. In this letter, we propose a modified Rsd extraction method that uses an optimized Id equation and a threshold voltage (Vth) extraction procedure for NWFETs. The Id equation is modified for the geometry of the NWFET, and Vth is obtained from the linear Y-function that can be observed in NWFETs because of volume inversion. A necessary assumption for this procedure is experimentally confirmed using the Y-function, and equations that fit the measured data perform well; this justifies the validity of applying the modified Id equations to NWFETs. Therefore, Rsd is perfectly extracted in all NWFETs and it is observed to be dependent on the channel diameter (dNW) when normalized by dNW, indicating that the extension resistance is the dominant component in the total Rsd. [ABSTRACT FROM PUBLISHER]

The low-frequency noise in the silicon nanowire field-effect transistor (SNWFET) is characterized using SNWFETs with different channel diameters dNW. The current density and the simulation result indicate that the volume inversion as manifested by the spatial charge distribution is enhanced in smaller dNW. The measured noise data are discussed based on the number and correlated mobility fluctuation model. It is shown that the low-frequency noise decreases in smaller dNW. This dNW-dependent noise behavior is clarified in terms of the effective oxide trap density and the fraction of inversion charges near the \Si–\SiO2 interface. [ABSTRACT FROM AUTHOR]

This letter proposes simple guidelines to design nanoscale fin-based multigate field-effect transistors (FinFETs) for radio frequency (RF)/analog applications in terms of fin height and fin spacing. Geometry-dependent capacitive and resistive parasitics are evaluated using analytic models and are included in a small-signal circuit. It is found that reducing the fin-spacing-to-fin-height ratio of FinFETs, as long as it is compatible with the process integration, is desirable for improving RF performance. This is because the current-gain cutoff frequency and the maximum oscillation frequency are affected by decreasing parasitic capacitance more than by increasing series resistance. [ABSTRACT FROM AUTHOR]

We performed 3D simulations to demonstrate structural effects in sub-20 nm gate-all-around silicon nanowire field effect transistors having asymmetric channel width along the channel direction. We analyzed the differences in the electrical and physical properties for various slopes of the channel width in asymmetric silicon nanowire field effect transistors (SNWFETs) and compared them to symmetrical SNWFETs with uniform channel width. In the same manner, the effects of the individual doping concentration at the source and drain also have been investigated. For various structural conditions, the current and switching characteristics are seriously affected. The differences attributed to the doping levels and geometric conditions are due to the electric field and electron density profile. [ABSTRACT FROM AUTHOR]

Fluoride ion (F–) and hydrofluoric (HF) acid are widely used, but they are highly toxic to the health and the natural environment. Sensors based on the field-effect transistor (FET) are commonly considered for chemical applications due to their small size and simple fabrication method. However, there has not been reported on the FET-based sensor for detecting F– ion and HF acid in the literature. Here, we demonstrate F– and HF acid sensors based on the FET, enabling sensitive detection in a small form factor. In particular, our FET sensor incorporates silicon nanosheet (SN) as the channel structure and polycrystalline lanthanum fluoride as a sensing membrane. Therefore, the fabricated sensor presents high responsivity (S R[M]) of 455.7 %/log[F–] for F– and high S R[M] of 392.4 %/log[HF] and has extremely low limit of detection of 10.20 ppb for F– and 32.04 ppb for HF acid. Moreover, it shows a good selectivity over other ions such as CO 3 2–, NO 3 –, PO 4 3–, and SO 4 2– and a low hysteresis current of 0.81 %. Finally, the performance of our HF sensor has been excellently demonstrated by the fabricated real-time HF sensor system and exhibits negligible error (less than 5 %) comparable to a commercial one. [Display omitted] • Sensitive F– and HF acid sensor is presented based on the SNFET and poly-LaF 3. • The fabricated sensor shows high response to F– with low LOD and high selectivity. • Sensitive HF acid detection are achieved by using the SNFET with TISAB solution. • A compact HF acid sensor system is demonstrated using the SNFET sensor. [ABSTRACT FROM AUTHOR]