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This study investigates the response of nanowire field-effect transistors (NWFETs) to total ionizing dose (TID), single-event transient (SET), and their coupling effects in junctionless (JL), inversion (IM), and junctionless accumulation (AC) modes. The degradation of the three modes under irradiation and the effect of device bias configuration on the electrical properties of NWFETs are analyzed, and the different effects of SET on the three modes are compared. On this basis, the influence of TID on SET current generation and the charge collection mechanism are studied, and the changes in peak current, pulse width, and collected charge of transient current under different TIDs are compared. The results show that JL mode has the worst resistance to TID and SET coupling effects, followed by IM and AC modes. [ABSTRACT FROM AUTHOR]

In this paper, an L-shaped tunneling field effect transistor (LTFET) with ferroelectric gate oxide layer (Si: HfO2) is proposed. The electric characteristic of NC-LTFET is analyzed using Synopsys Sentaurus TCAD. Compared with the conventional LTFET, a steeper subthreshold swing (SS = 18.4 mV/dec) of NC-LTFET is obtained by the mechanism of line tunneling at low gate voltage instead of diagonal tunneling, which is caused by the non-uniform voltage across the gate oxide layer. In addition, we report the polarization gradient effect in a negative capacitance TFET for the first time. It is noted that the polarization gradient effect should not be ignored in TFET. When the polarization gradient parameter g grows larger, the dominant tunneling mechanism that affects the SS is the diagonal tunneling. The on-state current (Ion) and SS of NC-LTFET become worse. [ABSTRACT FROM AUTHOR]

In this paper, a new Si/SiGe heterojunction tunneling field-effect transistor with a T-shaped gate (HTG-TFET) is proposed and investigated by Silvaco-Atlas simulation. The two source regions of the HTG-TFET are placed on both sides of the gate to increase the tunneling area. The T-shaped gate is designed to overlap with N pockets in both the lateral and vertical directions, which increases the electric field and tunneling rate at the top of tunneling junctions. Moreover, using SiGe in the pocket regions leads to the smaller tunneling distance. Therefore, the proposed HTG-TFET can obtain the higher on-state current. The simulation results show that on-state current of HTG-TFET is increased by one order of magnitude compared with that of the silicon-based counterparts. The average subthreshold swing (SS) of HTG-TFET is 44.64 mV/dec when V is varied from 0.1 to 0.4 V, and the point SS is 36.59 mV/dec at V = 0.2 V. Besides, this design cannot bring the sever Miller capacitance for the TFET circuit design. By using the T-shaped gate and SiGe pocket regions, the overall performance of the TFET is optimized. [ABSTRACT FROM AUTHOR]

Label-free biomolecular sensors have been widely studied due to their simple operation. L-shaped tunneling field-effect transistors (LTFETs) are used in biosensors due to their low subthreshold swing, off-state current, and power consumption. In a dielectric-modulated LTFET (DM-LTFET), a cavity is trenched under the gate electrode in the vertical direction and filled with biomolecules to realize the function of the sensor. A 2D simulator was utilized to study the sensitivity of a DM-LTFET sensor. The simulation results show that the current sensitivity of the proposed structure could be as high as 2321, the threshold voltage sensitivity could reach 0.4, and the subthreshold swing sensitivity could reach 0.7. This shows that the DM-LTFET sensor is suitable for a high-sensitivity, low-power-consumption sensor field. [ABSTRACT FROM AUTHOR]

The device structure of DLTFET is optimized by the Silvaco TCAD software to solve the problems of lower on-state current and larger miller capacitance of traditional doping-less tunneling field effect transistors (DLTFETs), and the performance can be greatly improved. Different from the traditional DLTFETs, the source region and pocket region of the doping-less TFET with the Ge/SiGe/Si hetero-junction and hetero-gate dielectric (H-DLTFET), respectively, use the narrow band-gap semiconductor Ge and SiGe materials, and the channel and drain region both use the silicon material. The H-DLTFET device use the Ge/SiGe hetero-junction engineering to decrease the tunneling barrier width, increase the band-to-band tunneling current, and obtain the higher current switching ratio and ultra-low sub-threshold swing (SS). Besides, the gate dielectric under auxiliary gate uses the low-k dielectric SiO2 material, which can effectively reduce the miller capacitance and improve the capacitance and frequency characteristics. The on-state current, switching ratio, trans-conductance, output current, and output conductance values of H-DLTFET can be increased by two, two, one, one, and one order of magnitude when compared with the DLTFET, respectively. Meanwhile, the point SS and average SS, respectively, decrease from 13 mV/Dec and 31.6 mV/Dec to 5 mV/Dec and 14.3 mV/Dec, and the gate-drain capacitance decrease from 0.99 fF/μm to 0.1 fF/μm. Besides, the cutoff frequency and gain bandwidth product of H-DLTFET are much larger than that of DLTFET, which can be explained by the excellent DC characteristics. The above simulation results show that the H-DLTFET has the better frequency characteristics, so it is more suitable for applications of ultra-low-power integrated circuits. [ABSTRACT FROM AUTHOR]

The two-dimensional materials can be used as the channel material of transistor, which can further decrease the size of transistor. In this paper, the molybdenum disulfide (MoS2) is grown on the SiO2/Si substrate by atmospheric pressure chemical vapor deposition (APCVD), and the MoS2 is systematically characterized by the high-resolution optical microscopy, Raman spectroscopy, photoluminescence spectroscopy, and the field emission scanning electron microscopy, which can confirm that the MoS2 is a monolayer. Then, the monolayer MoS2 is selected as the channel material to complete the fabrication process of the back-gate field effect transistor (FET). Finally, the electrical characteristics of the monolayer MoS2-based FET are tested to obtain the electrical performance. The switching ratio is 103, the field effect mobility is about 0.86 cm2/Vs, the saturation current is 2.75 × 10−7 A/μm, and the lowest gate leakage current is 10−12 A. Besides, the monolayer MoS2 can form the ohmic contact with the Ti/Au metal electrode. Therefore, the electrical performances of monolayer MoS2-based FET are relatively poor, which requires the further optimization of the monolayer MoS2 growth process. Meanwhile, it can provide the guidance for the application of monolayer MoS2-based FETs in the future low-power optoelectronic integrated circuits. [ABSTRACT FROM AUTHOR]

A high performance doping-less tunneling field effect transistor with Ge/Si0.6Ge0.4/Si heterojunction (H-DLTFET) is proposed in this paper. Compared to the conventional doping-less tunneling field effect transistor (DLTFET), the source and channel regions of H-DLTFET respectively use the germanium and Si0.6Ge0.4 materials to get the steeper energy band, which can also increase the electric field of source/channel tunneling junction. Meanwhile, the double-gate process is used to improve the gate-to-channel control. In addition, the effects of Ge content, electrode work functions, and device structure parameters on the performance of H-DLTFET are researched in detail, and then the above optimal device structure parameters can be obtained. Compared to the DLTFET, the simulation results show that the maximum on-state current, trans-conductance, and output current of H-DLTFET are all increased by one order of magnitude, whereas the off-state current is reduced by two orders of magnitude, so the switching ratio increase by three orders of magnitude. At the same time, the cut-off frequency and gain bandwidth product of H-DLTFET increase from 1.75 GHz and 0.23 GHz to 23.6 GHz and 4.69 GHz, respectively. Therefore, the H-DLTFET is more suitable for the ultra-low power integrated circuits. [ABSTRACT FROM AUTHOR]

To improve the on-state current and reduce the miller capacitance of the conventional junction-less tunneling field effect transistor (JLTFET), the junction-less TFET with Ge/Si0.3Ge0.7/Si heterojunction and heterogeneous gate dielectric (H-JLTFET) is investigated by the Technology Computer Aided Design (TCAD) simulation in this paper. The source region uses the narrow bandgap semiconductor material germanium to obtain the higher on-state current; the gate dielectric adjacent to the drain region adopts the low-k dielectric material SiO2, which is considered to reduce the gate-to-drain capacitance effectively. Moreover, the gap region uses the Si0.3Ge0.7 material to decrease the tunneling distance. In addition, the effects of the device sizes, doping concentration and work function on the performance of the H-JLTFET are analyzed systematically. The optimal on-state current and switching ratio of the H-JLTFET can reach 6 µA/µm and 2.6 × 1012, which are one order of magnitude and four orders of magnitude larger than the conventional JLTFET, respectively. Meanwhile, the gate-to-drain capacitance, off-state current and power consumption of the H-JLTFET can be effectively suppressed, so it will have a great potential in future ultra-low power integrated circuit applications. [ABSTRACT FROM AUTHOR]

In this paper, the performance comparisons of analog and radio frequency (RF) in the four different tunneling field effect transistors (TFETs) with the recessed channels are performed. The L-shaped channel TFET (LTFET), U-shaped channel TFET (UTFET), U-shaped channel with L-shaped gate TFET (LGUTFET) and U-shaped channel with dual sources TFET (DUTFET) are investigated by using Silvaco-Atalas simulation tool. The transconductance ( g m ), output conductance ( g ds ), gate capacitance ( C gg ), cut-off frequency ( f T ) and gain bandwidth product (GBW) are the parameters by analyzed. Among all the considered devices, the DUTFET has the maximum g m and g ds due to the improved on-state current by dual sources, and the LTFET has the minimum C gg because of the minimum gate-to-drain capacitance ( C gd ). Since analog/RF characteristics of a device are proportional to g m and inversely proportional to C gg , the LTFET and DUTFET have better analog/RF performance compared to the UTFET and LGUTFET. The extracted largest f T is 3.02 GHz in the LTFET and the largest GBW is 1.02 GHz in the DUTFET. The simulation results in this paper can be used as a reference to choose the TFET among these four TFETs for analog/RF applications. [ABSTRACT FROM AUTHOR]