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Multi-Channel Field-Effect Transistor (MCFET) structures with ultralow IOFF (16 pA/μm) and high ION (N: 2.27 mA/μm and P: 1.32 mA/μm) currents are obtained on silicon on insulator (SOI) with a high-k/metal gate stack, satisfying both low-standby-power and high-performance requirements. The experimental current gain of the MCFET structure is compared with that of an optimized planar FD-SOI reference with the same high-k/metal gate stack and is quantitatively explained by an analytical model. Transport properties are investigated, and the specific MCFET electrostatic properties are evidenced, in particular a higher VDsat for MCFETs compared with the planar reference. Finally, through 3-D numerical simulations correlated with specific characterizations, the influence of the channel width on the electrical performance is analyzed. For narrow devices, the parasitic bottom channel increases the total drain current of the MCFET structure without degrading the electrostatic integrity. [ABSTRACT FROM AUTHOR]

Three-dimensional Multi-Channel Field-Effect Transistor (MCFET) gate stack and series resistance are investigated and optimized by specifically developed integration processes, characterization methods, and numerical simulations. First, the impact of a TiN/HfO2 gate stack on embedded-gate MCFET structure performance is studied. Both TiN/SiO2 and N+poly-Si/SiO2 gate stacks were introduced in the MCFET to compare the carrier mobility behavior (300 K down to 20 K), the gate leakage current, and the negative bias temperature instability. The obtained electrical data are then compared with a planar FD-SOI reference, highlighting some specific challenges linked to the introduction of a high-k/metal gate stack in embedded cavities. On the other hand, it is shown how the series resistance is intrinsically increased by the 3-D configuration. We also show how this increase can be attenuated significantly by optimizing the source/drain (S/D) shape, the implantation conditions, and the S/D suicide position. [ABSTRACT FROM AUTHOR]

Using a new extraction methodology taking into account multisubband population and carrier degeneracy, we have experimentally determined backscattering coefficients, ballistic ratios, and injection velocities of n- and p-FDSOI devices with gate lengths down to 30 nm in the saturated and, for the first time, in the linear regimes. The evolution of these quasi-ballistic parameters is examined as a function of the inversion charge in the channel and at temperatures ranging from 50 to 293 K, showing stronger ballistic ratios in the saturated regime than in the linear one. We particularly focus on the linear regime, and a model linking ballisticity ratios and effective mobility is proposed and validated experimentally for different gate lengths. According to the experimental evaluation of the device mean-free path and its evolution with both the inversion charge in the channel and the temperature, we investigate the mobility degradation with decreasing gate lengths, highlighting the importance of Coulomb scattering on this unexpected mobility behavior. [ABSTRACT FROM AUTHOR]

Lateral size effects on surface-roughness-limited mobility in silicon-nanowire FETs are analyzed by means of a full-quantum 3-D self-consistent simulation. A statistical analysis is carried out by considering different realizations of the potential roughness at the Si-SiO2 interfaces. Nanowires with lateral section varying from 3 × 3 to 7 × 7 nm² are considered. Effective mobility is computed by evaluating the electron density in a reduced channel region to eliminate parasitic effects from contacts. It is found that transport in wires with the smallest section is dominated by scattering due to potential fluctuations, resulting in a larger standard deviation of the effective mobility, whereas it is dominated by transverse-mode coupling in wires with larger section, resulting in a stronger influence of surface roughness at high gate voltages. [ABSTRACT FROM AUTHOR]

This letter presents the first experimental study of the mobility in 50-nm gate length (LG) pMOSFETs highly strained by a contact etch stop layer. Thanks to an advanced characterization method, the mobility is in-depth studied versus the inversion charge density, the gate length and the temperature. The physical origin of the more than 50% mobility enhancement at LG = 50 nm is proven to be the low effective mass of the top valence band rather than any scattering modification. This mobility gain is maintained even at high effective field. This explains the 30% ION enhancement at 50-nm gate length, which is among the best results at such a dimension. [ABSTRACT FROM AUTHOR]