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The degradation of InSe film and its impact on field effect transistors are investigated. After the exposure to atmospheric environment, 2D InSe flakes produce irreversible degradation that cannot be stopped by the passivation layer of h-BN, causing a rapid decrease for InSe FETs performance, which is attributed to the large number of traps formed by the oxidation of 2D InSe and adsorption to impurities. The residual photoresist in lithography can cause unwanted doping to the material and reduce the performance of the device. To avoid contamination, a high-performance InSe FET is achieved by a using hard shadow mask instead of the lithography process. The high-quality channel surface is manifested by the hysteresis of the transfer characteristic curve. The hysteresis of InSe FET is less than 0.1 V at Vd of 0.2, 0.5, and 1 V. And a high on/off ratio of 1.25 × 108 is achieved, as well relative high Ion of 1.98 × 10−4 A and low SS of 70.4 mV/dec at Vd = 1 V are obtained, demonstrating the potential for InSe high-performance logic device. [ABSTRACT FROM AUTHOR]

A multivalued logic (MVL) device can achieve greater data density with a smaller footprint than a traditional binary logic device. In this study, a ternary logic inverter based on negative capacitance FETs (NCFETs) without additional footprints has been realized. By enhancing the amplification in surface potential owing to the utilization of the negative capacitance, the third intermediate state can be successfully obtained at VDD/2 in the conventional binary CMOS inverter. The third intermediate state arises due to no-saturation effect of drain current, and the noise margin of the third intermediate state (NMM) can be optimized by changing ferroelectric thickness or annealing temperature of ferroelectric material. The influence of remnant polarization (Pr) and coercive electric (EC) variation on the ternary logic inverter was investigated based on experimental data. Moreover, a ternary logic 8T SRAM with transmission gate logic (TGL) was proposed, and the results show that the proposed 8T SRAM cell exhibits nondestructive read and reliable write operations for all three states. [ABSTRACT FROM AUTHOR]

The negative-capacitance field-effect transistor (NCFET) is an emerging steep switching device that utilizes the negative capacitance of the ferroelectric layer to induce voltage amplification in the gate stack. In this study, an NCFET was fabricated by using a replacement metal gate process, which can avoid the influence of high temperature processes on ferroelectric film. The different sub-threshold slope (SS) characteristics of forward gate voltage sweep and reverse gate voltage sweep were investigated. The results show that the different SS characteristics may originate from asymmetrical polarization–voltage (P–V) hysteresis loops of metal–ferroelectric–insulator–silicon capacitance in the NCFET. Moreover, the influences of Hf/Zr ratio, annealing temperature and capacitance size on ferroelectric characteristics were investigated. The experimental results show that there is an optimal Hf/Zr ratio and annealing temperature that maximizes the residual polarization (Pr). For ferroelectric field-effect transistor (FeFET) memory design, the largest Pr should be chosen to increase retention time. For ferroelectric NCFET logic design, the negative capacitance can be adjusted by changing the Hf/Zr ratio and annealing temperature to achieve better capacitance matching between positive capacitance and negative capacitance. It is expected that experimental results may provide some guidance for the design and performance enhancement of FeFETs and NCFETs. [ABSTRACT FROM AUTHOR]

With the development of new designs and materials for nano-scale transistors, vertical Gate-All-Around Field Effect Transistors (vGAAFETs) with germanium as channel materials have emerged as excellent choices. The driving forces for this choice are the full control of the short channel effect and the high carrier mobility in the channel region. In this work, a novel process to form the structure for a VGAA transistor with a Ge channel is presented. The structure consists of multilayers of Si0.2Ge0.8/Ge grown on a Ge buffer layer grown by the reduced pressure chemical vapor deposition technique. The Ge buffer layer growth consists of low-temperature growth at 400 °C and high-temperature growth at 650 °C. The impact of the epitaxial quality of the Ge buffer on the defect density in the Si0.2Ge0.8/Ge stack has been studied. In this part, different thicknesses (0.6, 1.2 and 2.0 µm) of the Ge buffer on the quality of the Si0.2Ge0.8/Ge stack structure have been investigated. The thicker Ge buffer layer can improve surface roughness. A high-quality and atomically smooth surface with RMS 0.73 nm of the Si0.2Ge0.8/Ge stack structure can be successfully realized on the 1.2 µm Ge buffer layer. After the epitaxy step, the multilayer is vertically dry-etched to form a fin where the Ge channel is selectively released to SiGe by using wet-etching in HNO3 and H2O2 solution at room temperature. It has been found that the solution concentration has a great effect on the etch rate. The relative etching depth of Ge is linearly dependent on the etching time in H2O2 solution. The results of this study emphasize the selective etching of germanium and provide the experimental basis for the release of germanium channels in the future. [ABSTRACT FROM AUTHOR]