Search

We demonstrate nonvolatile and area-efficient ternary content-addressable memories (TCAMs) featuring amorphous indium–gallium–zinc–oxide (a-IGZO) ferroelectric field-effect transistors (FeFETs) with excellent electrical characteristics. An extremely large sensing margin of the TCAM array is achieved due to the large current ON/OFF ratio ($I_{ \mathrm{\scriptscriptstyle ON}}/I_{ \mathrm{\scriptscriptstyle OFF}})$ of the a-IGZO FeFETs. Our HfxZr $_{\text {1-x}}\text{O}$ 2 (HZO)-based a-IGZO FeFETs have a metal–ferroelectric–metal–insulator–semiconductor (MFMIS) structure. By engineering the area ratio of the ferroelectric layer (${A}_{Fe}$) and the metal–oxide–semiconductor layer (${A}_{MOS}$), a large memory window (MW) of 2.9 V is realized. Reliability test results, including retention, endurance, and positive bias temperature instability, show long-term retention of more than ten years and high endurance of 108 cycles. In addition, by scaling the channel length down to 40 nm, ON current of $77 ~\mu \text{A}/ \mu \text{m}$ (${V}_{\mathrm{GS}} - {V}_{\mathrm{TH}}$ = 5 V and ${V}_{\mathrm{DS}}$ = 2 V) and ${I}_{ \mathrm{\scriptscriptstyle ON}} / {I}_{ \mathrm{\scriptscriptstyle OFF}}$ of more than eight orders can be obtained for the ultrascaled a-IGZO FeFETs while maintaining an MW of 2.8 V. [ABSTRACT FROM AUTHOR]

In this letter, we demonstrate a complementary metal-oxide-semiconductor (CMOS) inverter comprising a germanium p-type field-effect transistor (Ge p-FET) and an amorphous indium-gallium-zinc-oxide n-type field-effect transistor ($\alpha $ -IGZO n-FET) on a SiO2/Si (OI) substrate. The key digital figure-of-merits of the CMOS inverter are evaluated, including voltage gain, noise margin (NM), and power consumption. The highest process temperature of this work is 400 °C to enable back-end-of-line (BEOL) compatible logic functions in three-dimensional (3D) monolithic integration. Performance advantages in terms of smaller subthreshold swing (SS) and higher mobility are also achieved as compared with previously reported p- and n-FETs in CMOS inverters comprising a p-FET and an n-FET with process temperature below 400 °C. The Ge p-FET exhibits a high-field mobility, threshold voltage (${V}_{\text {TH}}$), and SS of 91 cm2/ $\text{V}\cdot \text{s}$ , −0.26 V, 225 mV/decade, respectively, and those for the $\alpha $ -IGZO n-FET are 58 cm2/ $\text{V}\cdot \text{s}$ , 0.34 V, 163 mV/decade, respectively. The CMOS inverter shows a voltage gain of 5.5 V/V, NMH of 0.33 V, NML of 0.22 V, and power consumption of less than 0.03 mW at ${V}_{\text {DD}}$ of 1 V. [ABSTRACT FROM AUTHOR]

Germanium–tin (GeSn) p-channel fin field-effect transistor (p-FinFET) was realized on a novel GeSn-on-insulator (GeSnOI) substrate. The high-quality GeSnOI substrate was formed using direct wafer bonding technique and was layer-transferred from a 300-mm GeSn/Ge/Si donor wafer. Material quality was examined using atomic force microscopy, high-resolution transmission electron microscopy, Raman spectroscopy, and high-resolution X-ray diffraction. The fabricated GeSn p-FinFETs exhibit a small subthreshold swing (${S}$) of 79 mV/decade at ${V}_{\text {DS}}$ of −0.05 V (by a device with ${L}_{\text {CH}}$ of 200 nm and ${W}_{\text {Fin}}$ of 30 nm), good control of short channel effects, and high intrinsic transconductance (${G}_{m,\text {int}} = 702\,\,\mu \text {S}/\mu \text{m}$ at ${V}_{\text {DS}}$ of −0.5 V for ${L}_{\text {CH}}$ of 80 nm). Low-temperature mobility analysis was performed on the GeSn p-FinFETs. High effective hole mobility ($\mu _{\text {eff}}$) (210 cm2/ $\text {V}\cdot \text {s}$ at 290 K and 398 cm2/ $\text {V}\cdot \text {s}$ at 5 K) is achieved. The GeSn p-FinFETs presented in this paper exhibit the highest ${G}_{m,\text {int}}/{S}_{\text {sat}}$ at ${V}_{\text {DS}}$ of −0.5 V for all the reported GeSn p-FETs to date. [ABSTRACT FROM AUTHOR]