Search

This work substantiates the impact of Gaussian doping on the electrical performance of double gate junctionless field-effect transistor (DG-JLFET). To get a better understanding of the influence of non-uniform doping, the device is compared with uniform-doped DG-JLFET with various concentrations. The device is later used to demonstrate its usability in six-transistor static random access memory (6T SRAM) bitcell by studying the performance metrics, i.e. stability noise margin and write delay. A comparison of performance metrics is also given with uniformly doped DG-JLFET-based-6T SRAM. Improvement in static noise margin was observed with Gaussian doping without compromising with write access time. [ABSTRACT FROM AUTHOR]

In this paper, we systematically examined the impact of fin height ( H\mathrm{ Fin} ) and fin angle ( \theta \mathrm{ Fin} ) on the ac performance parameters including total gate capacitance ( C\mathrm{ gg} ), RC delay ( C_{\mathrm{ gg}}V_{\mathrm{ DD}}/I_{\mathrm{\scriptscriptstyle ON}} ), cutoff frequency ( f_{T} ), energy ( E ), total power ( P_{\mathrm{ Total}} ), and leakage power ( P_{\mathrm{ Leakage}} ) of hybrid FinFETs at the supply voltage, V\mathrm{ DD} with on-current I\mathrm{\scriptscriptstyle ON} . The RC delay, energy, and total power consumption are the primary factors limiting the operating frequency of the high-performance devices. Therefore, these electrical parameters are needed to be addressed in the architectural level of the fin based devices. In this paper, a calibrated numerical device simulation tool is used to achieve the best device performances of 14-nm hybrid FinFETs. From the simulated current–voltage ( I – V ) and capacitance–voltage ( C – C\mathrm{ gg}V\mathrm{ DD}/I\mathrm{\scriptscriptstyle ON} , fT , CV2, P\mathrm{ Total} , and P\mathrm{ Leakage} are extracted to analyze the effect of H\mathrm{ Fin} and \theta \mathrm{ Fin} on the performance matrices of these devices. In addition, this paper proposes an optimum structural configuration for 14-nm hybrid FinFET architecture for digital application perspective. [ABSTRACT FROM AUTHOR]