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A new low‐power and high‐speed multiplier is presented based on the voltage over scaling (VOS) technique and new 5:3 and 7:3 counter cells. The VOS reduces power consumption in digital circuits, but different voltage levels of the VOS increase the delay in different stages of a multiplier. Hence, the proposed counters are implemented by the gate‐diffusion input technique to solve the speed limitation of the VOS‐based circuits. The proposed GDI‐based 5:3 and 7:3 counters save power and reduce the area by 2x and 2.5x, respectively. To prevent the threshold voltage (Vth) drop in the suggested GDI‐based circuits, carbon nanotube field‐effect transistor (CNTFET) technology is used. In the counters, the chirality vector and tubes of the CNTFETs are properly adjusted to attain full‐swing outputs with high driving capability. Also, their validation against heat distribution under different time intervals, as a major issue in the CNTFET technology is investigated, and their very low sensitivity is confirmed. The low complexity, high stability and efficient performance of the presented counter cells introduce the proposed VOS‐CNTFET‐GDI‐based multiplier as an alternative to the previous designs. [ABSTRACT FROM AUTHOR]

Summary: The performance of the programmable integrated circuits (ICs) like digital signal processors (DSPs), central processing units (CPUs), and microcontrollers is highly dependent on the magnitude comparators. This article presents a new reliable and efficient 1‐bit comparator based on carbon nanotube field‐effect transistors (CNTFETs) technology. The gate diffusion input (GDI) technique is used to reduce the number of transistors. Also, single swing restoration (SR) transistors and transmission gate (TG) techniques are combined to attain full‐swing outputs with high driving capability. The low internal capacitances and the fewer number of internal nodes of the proposed comparator make it low‐power both in single‐bit and multibit (2‐bit, 4‐bit, 8‐bit, and 16‐bit) implementations. Variations analyses of the circuit and technology parameters are performed that show the cell efficiency. From the layout results, the 1‐bit and 16‐bit comparators occupy 0.1944 μm2 and 37.485 μm2 as the total die area, respectively. The proposed circuit is implemented in image processing in which the best performance compared with state‐of‐the‐art designs regarding hardware complexity, circuitry performance, and image quality assessments are confirmed, by at least 50% improvements of different critical parameters. The resulted figure of merits nominates the cell for future ICs. [ABSTRACT FROM AUTHOR]

• Using the carbon nanotube field-effect transistors technology to design approximate arithmetic circuits. • The gate diffusion input and dynamic threshold techniques are integrated to attain efficient circuits. • The presented approximate full adders show reliable performance during image processing. • The approximate full adders applied in bioimage processing. • Fat and water can be detected in bioimages by the presented approximate cells. Two new approximate full adders (FAs) are proposed by the multiplexers (MUXs) and OR gates with the gate diffusion input (GDI) technique. The cells are named GDI-based MUX approximate FAs (GMAFAs), GMAFA1, and GMAFA2. The threshold voltage drop of the GDI-based circuits is solved by carbon nanotube field-effect transistors (CNTFETs) technology and the dynamic threshold (DT) technique. The FAs have accurate C out , approximate Sum, and a low number of transistors. They are low-power, high-speed, and energy-efficient for ripple-carry adders (RCAs). The GMAFA1 and GMAFA2 have a total area of 0.068 µm2 and 0.119 µm2, respectively, which demonstrate 27.8% and 54.55% improvement in power-delay-area-product (PDAP) in comparison with the best references. The results of error distance (ED), normalized mean error distance (NMED), power signal-to-noise ratio (PSNR), and energy-saving confirm the accuracy of the presented cells for image processing applications. [Display omitted] [ABSTRACT FROM AUTHOR]

• Using the gate diffusion input technique in a new approximate full adder. • The full adder is implemented by carbon nanotube field-effect transistors. • The dynamic threshold technique improves the full adder swing. • A new approximate subtractor implemented by the full adder. • The approximate full adder and subtractor detect brain stroke. Approximate circuits are used in fault-tolerance applications, where carbon nanotube field-effect transistor (CNTFET) technology assists to achieve high performance. In this study, a new 8-transistor approximate full adder (FA) is designed and implemented using CNTFETs based on the gate diffusion input (GDI) technique. The FA is implemented in a ripple carry adder (RCA) and a 4-bit inexact subtractor for bioimages difference detection and finally stroke recognition. The non-full-swing outputs of the presented GDI cells are obviated by the dynamic threshold (DT) technique. The presented FA consumes a power of 2.0446 µW, while its power-delay-product (PDP) is 6.4536 fJ. Also, the superior results of peak signal-to-noise ratio (PSNR), power consumption, and PDP of the proposed subtractor are 30.866 dB, 9.642 µW, and 314.907 fJ, respectively. The FA has an area of 0.161 µm2 while the 4-bit subtractor occupies 2.18 µm2. The presented circuits show efficient performance for bioelectronics integrated circuits (ICs). [Display omitted] [ABSTRACT FROM AUTHOR]

Summary: Sophisticated systems take advantage of approximate circuits for energy management. A gate‐level structure is introduced to make a novel imprecise full adder (FA) cell by the gate diffusion input (GDI) strategy. The carbon nanotube field‐effect transistor (CNTFET) technology lowers the FA power, and the swing issue is resolved by the dynamic threshold (DT) technique. The FA specifications are 10 transistors, two internal nodes, 0.191‐μm2 area, three errors, and an error rate (ER) of 37.5%. Some inputs are directly passed to the final stage of the FA to reduce the delay and dynamic power. The FA is used in three 4:2 compressors with 12, 16, and 20 transistors, respectively. The compressors are based on the modified stacking concept to attain low power, small area, and high speed. The compressors are used up in the partial product reduction tree (PPRT) of a new 8‐bit inexact multiplier. Regarding the multiplier, the power–delay product (PDP) is decreased by 25.21%, and the normalized mean error distance (NMED) shows high accuracy. An imprecise discrete cosine transform (DCT) is implemented by the multiplier for image compression, and compared with the literature, the peak signal‐to‐noise ratio (PSNR) and structural similarity index metric (SSIM) are amended by 8.26% and 7.29%, respectively. [ABSTRACT FROM AUTHOR]

Here, a new 4:2 approximate compressor is presented by the gate diffusion input (GDI) technique. Although GDI cells suffer from threshold voltage drop, the dynamic threshold approach and carbon nanotube field‐effect transistors are merged to overcome the mentioned problem. The proposed cell has full‐swing outputs, while its error and power delay product are at low rates. Therefore, low voltage multipliers that are used in image processing can benefit from the proposed compressor. [ABSTRACT FROM AUTHOR]

Three new approximate subtractors are presented based on the gate diffusion input (GDI) technique which benefits from the dynamic threshold (DT) technique using carbon nanotube field-effect transistors (CNTFETs) technology. Proposed-1, Proposed-2, and Proposed-3 subtractors have 10, 8, and 6 transistors with a total area of 0.289 μm2, 0.123 μm2, and 0.065 μm2, respectively. In Proposed-1 and Proposed-2, only XOR and F1 gates are used, which respectively have 2 and 4 errors. To solve the non-full-swing defects of these two circuits, only three F2-GDI gates are used in the Proposed-3, which has 4 errors. The Proposed-1 gives 0.25 as error distance (ED) while two other circuits with a lower area have an ED of 0.5. The Proposed-3 has a simple, low-power, and ground-free structure. The subtractors are implemented in an 8 to 4 non-restoring divider in four different configurations including vertical, horizontal, square, and triangular. The drivers based on Proposed-2 and Proposed-3 are the best circuits with average power-delay-product (PDP) savings of 68.16% and 57.43%, respectively. Finally, the dividers are used in the change detection of medical images, where, the proposed circuits show better circuitry performance and image quality production. [ABSTRACT FROM AUTHOR]