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Highly sensitive, low-power, and chip-scale H2 gas sensors are of great interest to both academia and industry. Field-effect transistors (FETs) functionalized with Pd nanoparticles (PdNPs) have recently emerged as promising candidates for such H2 sensors. However, their sensitivity is limited by weak capacitive coupling between PdNPs and the FET channel. Herein we report a nanoscale FET gas sensor, where electrons can tunnel between the channel and PdNPs and thus equilibrate them. Gas reaction with PdNPs perturbs the equilibrium, and therefore triggers electron transfer between the channel and PdNPs via trapping or de-trapping with the PdNPs to form a new balance. This direct communication between the gas reaction and the channel enables the most efficient signal transduction. Record-high responses to 1–1000 ppm H2 at room temperature with detection limit in the low ppb regime and ultra-low power consumption of ~ 300 nW are demonstrated. The same mechanism could potentially be used for ultrasensitive detection of other gases. Our results present a supersensitive FET gas sensor based on electron trapping effect in nanoparticles. Highly sensitive, low-power, and chip-scale gas sensors are of great interest to both academia and industry. The authors developed a nanotransistor-based gas sensor with high sensitivity enabled by electron trapping effect in nanoparticles. [ABSTRACT FROM AUTHOR]

Random trapping and detrapping of charged carriers in the vicinity of gate oxide/Si interface has for long been considered as the dominant noise source in Si nanowire (SiNW) FET-based biochemical sensors. Here we extend our previous work presenting a Schottky junction tri-gate SiNWFETs (SJGFET) fabricated on a bonded silicon-on-insulator (SOI) substrate, aiming for ultra-low device noise generation. The SJGFET exhibits near-ideal gate coupling efficiency with a subthreshold swing of ~66 mV/dec. Its gate-referred voltage noise, Svg, are 1.2 × 10−10 and 1.1 × 10−11 V2 μm2/Hz at 1 and 10 Hz, respectively. These Svg values are significantly lower than that of previously reported FET-based sensors. More importantly, Svg of the SJGFET are below the reported voltage noise generated by the oxide/electrolyte sensing interface. Using our SJGFET as the signal transducer can greatly relieve the concern of the adverse effect from the intrinsic device noise in biochemical sensing applications. [ABSTRACT FROM AUTHOR]

This letter presents a systematic study of how the substrate bias (${V}_{\text {sub}}$) modulation affects the current-voltage (${I}$ - ${V}$) characteristics and low-frequency noise (LFN) of lateral bipolar junction transistors (LBJTs) fabricated on a silicon-on-insulator (SOI) substrate. The current gain ($\beta$) of npn LBJTs at low base voltage can be greatly improved by a positive ${V}_{\text {sub}}$ as a result of enhanced electron injection into the base near the buried oxide (BOX)/silicon interface. However, an excessive positive ${V}_{\text {sub}}$ may also adversely affect the LFN performance by amplifying the noise generated as a result of carrier trapping and detrapping at that interface. Our results provide a practical guideline for improving both $\beta $ and the overall noise performance when using our LBJT as a local signal amplifier. [ABSTRACT FROM AUTHOR]

Silicon nanowire (SiNW) field-effect transistors (SiNWFETs) are of great potential as a high-sensitivity charge sensor. The signal-to-noise ratio (SNR) of an SiNWFET sensor is ultimately limited by the intrinsic device noise generated by carrier trapping/detrapping processes at the gate oxide/silicon interface. This carrier trapping/detrapping-induced noise can be significantly reduced by replacing the noisy oxide/silicon interface with a Schottky junction gate (SJG) on the top of the SiNW. In this paper, we present a tri-SJG SiNWFET (Tri-SJGFET) with the SJG formed on both the top surface and the two sidewalls of the SiNW so as to enhance the gate control over the SiNW channel. Both experiment and simulation confirm that the additional sidewall gates in a narrow Tri-SJGFET indeed can confine the conduction path within the bulk of the SiNW channel away from the interfaces and significantly improve the immunity to the traps at the bottom buried oxide/silicon interface. Therefore, the optimal low-frequency noise performance can be achieved without the need for any substrate bias. This new gating structure holds promises for further development of robust SiNWFET-based charge sensors with low noise and low operation voltage. [ABSTRACT FROM AUTHOR]

Ferroelectric and negative-capacitance field-effect transistors (FeFETs and NCFETs) have recently garnered great attention as devices for applications in memory and low-power logic, respectively. As these technologies are pursued, it is critical to have a variety of measurement approaches, including methods familiar to the electron-device and microwave communities that can aid in fully understanding the behavior of ferroelectrics in FeFETs and NCFETs. In this paper, we propose and show the viability of using frequency-domain electrical measurement techniques employing the well-known microwave S-parameters, and their large-signal generalization and X-parameters. Our methods provide the means to trace the intrinsic polarization versus electric-field curve of the ferroelectric, i.e., with the parasitics de-embedded, thereby showing the innate ferroelectric response, which cannot be done using conventional techniques. These methods also enable extraction of all the parameters of the Landau–Khalatnikov equation, which is commonly used to model ferroelectric behavior in FeFETs and NCFETs. This paper hence takes a useful step toward methods familiar to the electron-device community that can help to better understand and optimize FeFET and NCFET technologies. [ABSTRACT FROM AUTHOR]

It has recently been suggested that ferroelectric (FE) negative capacitance effects can be used to achieve steep subthreshold slope field-effect transistors, which are greatly desired for reducing energy consumption in modern digital electronics. Here, we propose that this concept can be improved by the introduction of a very thin metal or metal-like layer (a quantum metal) between the FE and the semiconductor channel. We show how to design this layer so that it attenuates the polarization charge of the FE, applying an appropriate charge to the semiconductor, while at the same time presenting a relatively constant capacitance to the FE layer, as is needed to stabilize the negative capacitance regime. For homogeneous polarization, we estimate that this device (a QMFeFET) can have extremely steep subthreshold characteristics (2 mV/decade over 11 decades) and that its energy and delay performance are advantageous. [ABSTRACT FROM AUTHOR]

Experimental-modeling investigation of the transient thermal crosstalk between the field-effect transistors implemented on a silicon-on-insulator substrate is reported. The measurements were performed using a high-speed electrical pulse—probe sampling technique, which allowed detection of thermally modulated subthreshold currents. The technique achieved a temperature resolution of ∼50 mK, a time resolution of 5 ns, and a temperature sensitivity of ∼0.6 μA/K. The finite-element method was used to solve the heat diffusion equation and to obtain the temperature profiles for the given device structures. The combined high-resolution experimental—simulation approach allowed the study of the thermal crosstalk between two adjacent devices and probe the local temperature at different locations of the structure. The effects of the interface quality, layer thickness, material selection, and interdevice spacing on the heat diffusion and device performance were investigated in detail. [ABSTRACT FROM AUTHOR]

Various nonplanar, multigate field-effect transistors (FET) structures have been reported that offer better gate con- trol than planar MOSFETs. In the nanometer regime, however, multigate (nanowire) structures also suffer strong quantum con- finement, which causes deleterious effects such as large threshold voltage variation. In this paper, we propose a general approach to compare planar versus nonplanar FETs with the consideration of both electrostatic integrity (gate control) and quantum confinement (the so-called "EQ approach"). With this EQ approach, we show that the cylindrical wire FET and the planar double-gate MOSFET have approximately equal scaling capability for a (001)-oriented wafer, while the nonplanar wire structures are significantly better for other wafer orientations [e.g., (011)] where the effective mass in the confinement direction of the planar MOSFET is relatively small. [ABSTRACT FROM AUTHOR]

The electrical characteristics of a heterojunction tunneling field-effect transistor (HETT), with a p-type \Si0.75\Ge0.25 source, have been measured as a function of strain. HETTs with channel transport and applied strain both in the [110] direction show a smooth monotonic change in drain current over a range of 0.09% compressive to 0.13% tensile strain. A measure \gamma = (d/d\ln JD)(d\ln JD/ds)\verts = 0 of the effect of strain s on tunneling current JD is proposed, which captures the dependence of the tunneling exponential argument on strain. An experimental value of \gamma = - \11.7 is extracted for the tensile case and compared to simulation results. We found theoretically that the value and sign of \gamma depend sensitively on the built-in strain at the Si–SiGe interface. [ABSTRACT FROM AUTHOR]

In the article the authors reflect on increasing the speed of computers by improving field-effect transistors. They assert that electronic companies are shrinking the transistor and increasing the number of parallel processors which results in power dissipation and heat generation. They opine that improving the operation of transistors means altering the switching behavior so less gate voltage is needed to turn the device on and off.

The article reports that the excellent electrical properties of single-walled carbon nanotubes (SWCNT) make them the most promising candidate for creating transistors on a scale smaller than can be achieved with silicon. A field-effect transistor (FET), which is the basic component of present computer circuitry, has been demonstrated based on individual SWCNTs. This achievement would demonstrate that SWCNTs can be used as a basis for electronics, similar to the way silicon wafers are currently used. A ring oscillator is the ultimate test for new materials in high-frequency ac applications and for evaluating their compatibility with conventional circuit architectures. In a CMOS inverter, both an n-type FET and a p-type FET are needed to realize a basic logic function. An extra inverter stage, which eliminates interference between the measurement setup and the oscillator operation, follows the ring oscillator portion to allow for the signal to be read by a spectrum analyzer.