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It has recently been suggested that ferroelectric (FE) negative capacitance effects can be used to achieve steep subthreshold slope field-effect transistors, which are greatly desired for reducing energy consumption in modern digital electronics. Here, we propose that this concept can be improved by the introduction of a very thin metal or metal-like layer (a quantum metal) between the FE and the semiconductor channel. We show how to design this layer so that it attenuates the polarization charge of the FE, applying an appropriate charge to the semiconductor, while at the same time presenting a relatively constant capacitance to the FE layer, as is needed to stabilize the negative capacitance regime. For homogeneous polarization, we estimate that this device (a QMFeFET) can have extremely steep subthreshold characteristics (2 mV/decade over 11 decades) and that its energy and delay performance are advantageous. [ABSTRACT FROM AUTHOR]

Experimental-modeling investigation of the transient thermal crosstalk between the field-effect transistors implemented on a silicon-on-insulator substrate is reported. The measurements were performed using a high-speed electrical pulse—probe sampling technique, which allowed detection of thermally modulated subthreshold currents. The technique achieved a temperature resolution of ∼50 mK, a time resolution of 5 ns, and a temperature sensitivity of ∼0.6 μA/K. The finite-element method was used to solve the heat diffusion equation and to obtain the temperature profiles for the given device structures. The combined high-resolution experimental—simulation approach allowed the study of the thermal crosstalk between two adjacent devices and probe the local temperature at different locations of the structure. The effects of the interface quality, layer thickness, material selection, and interdevice spacing on the heat diffusion and device performance were investigated in detail. [ABSTRACT FROM AUTHOR]

Various nonplanar, multigate field-effect transistors (FET) structures have been reported that offer better gate con- trol than planar MOSFETs. In the nanometer regime, however, multigate (nanowire) structures also suffer strong quantum con- finement, which causes deleterious effects such as large threshold voltage variation. In this paper, we propose a general approach to compare planar versus nonplanar FETs with the consideration of both electrostatic integrity (gate control) and quantum confinement (the so-called "EQ approach"). With this EQ approach, we show that the cylindrical wire FET and the planar double-gate MOSFET have approximately equal scaling capability for a (001)-oriented wafer, while the nonplanar wire structures are significantly better for other wafer orientations [e.g., (011)] where the effective mass in the confinement direction of the planar MOSFET is relatively small. [ABSTRACT FROM AUTHOR]

The electrical characteristics of a heterojunction tunneling field-effect transistor (HETT), with a p-type \Si0.75\Ge0.25 source, have been measured as a function of strain. HETTs with channel transport and applied strain both in the [110] direction show a smooth monotonic change in drain current over a range of 0.09% compressive to 0.13% tensile strain. A measure \gamma = (d/d\ln JD)(d\ln JD/ds)\verts = 0 of the effect of strain s on tunneling current JD is proposed, which captures the dependence of the tunneling exponential argument on strain. An experimental value of \gamma = - \11.7 is extracted for the tensile case and compared to simulation results. We found theoretically that the value and sign of \gamma depend sensitively on the built-in strain at the Si–SiGe interface. [ABSTRACT FROM AUTHOR]

In the article the authors reflect on increasing the speed of computers by improving field-effect transistors. They assert that electronic companies are shrinking the transistor and increasing the number of parallel processors which results in power dissipation and heat generation. They opine that improving the operation of transistors means altering the switching behavior so less gate voltage is needed to turn the device on and off.

The article reports that the excellent electrical properties of single-walled carbon nanotubes (SWCNT) make them the most promising candidate for creating transistors on a scale smaller than can be achieved with silicon. A field-effect transistor (FET), which is the basic component of present computer circuitry, has been demonstrated based on individual SWCNTs. This achievement would demonstrate that SWCNTs can be used as a basis for electronics, similar to the way silicon wafers are currently used. A ring oscillator is the ultimate test for new materials in high-frequency ac applications and for evaluating their compatibility with conventional circuit architectures. In a CMOS inverter, both an n-type FET and a p-type FET are needed to realize a basic logic function. An extra inverter stage, which eliminates interference between the measurement setup and the oscillator operation, follows the ring oscillator portion to allow for the signal to be read by a spectrum analyzer.