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In this article, the degradation mechanism of the Ge N+-P junctions with a thin GeSn surface layer is investigated, aiming for source/drain (S/D) application in emerging field-effect transistors. GeSn is a promising channel material with high carrier mobility, which can offer a better performance of the field-effect transistors. By performing thermal annealing at different temperatures, the reverse-biased leakage current increases apparently when annealing temperature exceeds 550 °C. X-ray diffraction (XRD) analysis indicates most Sn atoms escape from lattice sites while secondary-ion mass spectroscopy (SIMS) analysis indicates enhanced Sn diffusion in Ge bulk after ion implantation. Therefore, a degradation model considering Sn-defects interaction is proposed to explain the degradation of junction leakage current and possible solution is proposed. [ABSTRACT FROM AUTHOR]

The tunnel field-effect transistor (FET) is a promising candidate for use in ultralow-power applications because of its distinct operation principle, namely, band to band tunneling (BTBT). However, the ON-state current of the tunnel device is extremely low because of the poor tunneling efficiency of the BTBT. In this paper, a novel epitaxial tunnel layer (ETL) structure combining vertical tunneling orientation was proposed. The ETL structure performs more favorably than does the traditional lateral tunnel FET structure in an all-silicon device. By using low bandgap materials in the ETL, the ON-state BTBT current increases and an extremely low intrinsic OFF-state current is maintained because of the small low bandgap junction area. The onset voltage of the bipolar BTBT can also be postponed using ETL band engineering. The optimized parameters of the Six\rm Ge1\-{\rm x} ETL tunnel FET structure increase the ON-state current 10^7\--10^8 times compared with that of the traditional lateral silicon tunnel FET. The minimal subthreshold swing (SS) and ON/OFF current ratio also improve, the SS decreases from 47 mV/decade to 29 mV/decade, and the ON/OFF current ratio increase from 10^5 to 10^10. In this paper, the effects of the ETL parameters on device performance are discussed in detail. [ABSTRACT FROM PUBLISHER]

Abstract: Carbon nanotube field effect transistors (CNTFETs) have been considered as one of the potential candidates for nanoelectronics beyond Si CMOS. However, it is not easy to have high performance CNTFETs with high yield currently. In this work, we proposed a local bottom-gate (LBG) CNTFETs combined with a novel device concept and optimized process technologies. High performance of CNTFET with low subthreshold swing of 139mV/dec, high transconductance of 1.27μS, and high I on/I off ratio of 106 can be easily obtained with Ti source/drain contact after a post annealing process. Record high yield of 74% has been demonstrated. On the basis of the proposed process, lots of high performance CNTFETs can be obtained easily for advanced study on the electrical characteristics of CNTFETs in the future. [Copyright &y& Elsevier]

The gate-to-source capacitance ( C\mathrm {GS}) in the p-channel tunnel FET (pTFET) with a Ge epitaxial tunnel layer (ETL) structure is investigated. The characteristic of C\mathrm {GS} is revealed and studied with various frequencies and temperatures. Due to the highly efficient band-to-band tunneling (BTBT) in the Ge ETL pTFET, the minority carriers for the source can be generated by the BTBT process and can respond with the gate voltage. Therefore, the contribution of C\mathrm {GS} to the total gate capacitance in the ON-state would increase, which results in a decrease of the gate-to-drain capacitance. This property is beneficial to the suppression of the Miller capacitance effect on the TFET-based circuit. [ABSTRACT FROM AUTHOR]

Fringing-induced barrier lowering (FLBL) effect on nanoscale MOSFET is comprehensively examined. It is observed that by combining stack gate dielectric, conductive spacer, shod sidewall spacer, and minimum gate/drain (G/D) overlap, the Ioff with a dielectric constant of (k) 100 is only 1.6 times higher than that with k = 3.9 when the gate length is 25 nm. The fully depleted silicon-on-insulator device shows even better FLBL immunity. It is concluded that although the FIBL effect can not be eliminated, it would not an issue beyond the 45-nm technology node. [ABSTRACT FROM AUTHOR]

Although high channel electron mobility has been reported after some passivation techniques, the performance of n-channel Ge metal-oxide-semiconductor field-effect transistor is still limited by the high Schottky barrier height at the metal/n-Ge contact interface, which comes from the Fermi level pinning effect. Recent experiments demonstrated that the Schottky barrier height can be reduced by inserting a thin dielectric layer between metal and Ge. However, the mechanism has not been well clarified. In this paper, the metal induced gap state model, the dipole layer model, and the fixed charge model are verified by varying contact metals, dielectric thicknesses, as well as the annealing temperatures. The pinning factor is improved slightly by dielectric insertion but its value is independent of the dielectric thickness and is still much lower than the ideal value of the non-pinning case. This pinning effect is consistent with the Fermi level pinning at the metal/TiO2 interface. After thermal process, no interfacial layer forms at the TiO2/Ge interface and the TiO2 crystallizes gradually after annealing but the Schottky barrier height increases. Since the amount of fixed charges in the thin dielectric layer estimated from a metal-insulator-semiconductor structure is about 2 × 1011 cm-2 and is insufficient to produce the observed 0.5 eV Schottky barrier height reduction, it is thus recommended that the main mechanism comes from the change of interface dipoles and the annealing effect is attributed to the short-range ordering of the TiO2 layer. Furthermore, dielectric with low conduction band offset which has good thermal stability should be explored. [ABSTRACT FROM AUTHOR]