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An analytical model of parasitic capacitancein inserted-oxide FinFETs (iFinFETs) is proposed. A comparative study on the parasitic capacitance of contemporary multigate devices conforming to 7-nm technology node targets is presented. The proposed model is validated against 3-D Technology Computer-Aided Design (TCAD) simulations. Dependence of the iFinFET parasitic capacitance on device design parameters, such as the inserted-oxide thickness (Tiox) and inserted-oxide recess (Trec), is shown using the proposed model and TCAD simulations. [ABSTRACT FROM AUTHOR]

We examine the impact of line-edge roughness (LER) on the variability in the on-current and saturation threshold voltage of ultrascaled FinFET devices via quantum-mechanical transport simulation. We obtain a realistic model of LER by decomposing the LER into short- $\lambda $ and long- $\lambda $ fluctuations, and we consider their separate influences on device performance. We show that the long- $\lambda $ fluctuations lead to greater device variability than the short- $\lambda $ fluctuations, and we explain the difference between the two cases via the influence of fluctuating quantum confinement arising from the LER. Finally, we consider devices in which the long- $\lambda $ fluctuations of the two fin edges are correlated and demonstrate that this correlation significantly improves the variability. Thus, we show the continued need for fabrication technology either to reduce the amplitude of the long- $\lambda $ fluctuations or to ensure the long- $\lambda $ fluctuations between the sidewalls of ultrascaled FinFET devices are correlated. [ABSTRACT FROM AUTHOR]