Search

This article reports Si-passivated Ge nFinFETs with significantly improved GmSAT/SSSAT and positive bias temperature instability (PBTI) reliability enabled by an improved replacement metal gate (RMG) high-k last process. SiO2 dummy gate oxide (DGO) deposition on Ge fin is shown to form (Six)Ge1-xOy, which is, compared to a pure SiO2, more difficult to remove completely during the dry clean prior to the gate-stack formation. By extending the DGO removal clean, improved PBTI reliability, reduced DIT, and increased electron mobility are demonstrated. Moreover, by suppressing the Ge channel oxidation through the choice of less-oxidizing DGO or inserting an Si-cap layer prior to the DGO deposition, a greatly improved long-channel electron mobility is obtained at a scaled fin width. Finally, together with the PBTI maximum VOV of 0.13 V, the best GmSAT/SSSAT of 5.4 is achieved, which is today’s record value among the sub-100-nm-Lg n-channel Ge Fin and gate-all-around nanowire FETs. These results clearly show the importance of the pre-gate-stack channel surface preparation on the scaled Ge FinFETs to benefit from a previously optimized Si-passivated Ge gate-stack. [ABSTRACT FROM AUTHOR]

This paper reports on 45-nm fin pitch strained p-type Ge gate-all-around devices fabricated on 300-mm SiGe strain-relaxed-buffers (SRB). By improving the process integration flow, excellent electrical performance is demonstrated: the $Q$ factor is increased to 25 as compared to our previous work, $I_{ \mathrm{\scriptscriptstyle ON}} = \textsf {500}~\mu \text{A}/ \mu \text{m}$ at $I_{ \mathrm{\scriptscriptstyle OFF}} = \textsf {100}$ nA/ $\mu \text{m}$ is achieved, approaching the best published results on Ge finFETs. Good negative-bias temperature instability reliability is also maintained, thanks to the use of Si-cap passivation. The process flow developed for the fabrication of the single Ge nanowire (NW) is adapted and vertically stacked strained Ge NWs featuring 8-nm channel diameter are successfully demonstrated. A systematic analysis of the strain evolution is conducted on both single and double Ge NWs after the most challenging steps of the process integration flow: 1.7-GPa uniaxial-stress is demonstrated along the Ge wire, which originates from the lattice mismatch between the Ge source/drain and the Si0.3Ge0.7 SRB. [ABSTRACT FROM AUTHOR]

The total ionizing dose (TID) response of bulk FinFETs is investigated for various geometry variations, such as fin width, channel length, and fin pitch. The buildup of oxide-trapped charge in the shallow trench isolation turns on a parasitic transistor, leading to increased leakage current (higher IOFF.) The TID-induced degradation increases with decreasing fin width. Transistors with longer channels degrade less than those with shorter channels. Transistors with large fin pitch degrade more, compared to those with narrow fin pitch. TCAD simulations are used to analyze the buildup of trapped charge in the trench isolation oxide and its impact on the increase in leakage current. The strong influence of charge in the STI in narrow-fin transistors induces a parasitic leakage current path between the source and the drain, while in wide-fin devices, for the same amount of trapped charge in the isolation oxide, the subsurface leakage path is less effective. [ABSTRACT FROM PUBLISHER]

In this work, we will give an overview of the innovations in materials and new device concepts that will be needed to continue Moore’s law to the sub-10 nm technology nodes. To meet the power and performance requirements high mobility materials in combination with new device concepts like tunnel FETs and gate-all-around devices will need to be introduced. As the density is further increased and it becomes increasingly difficult to put contacts, spacers and gate in the available gate pitch, disruptive integration schemes such as vertical transistors and monolithic 3D integration might lead the way to the ultimate scaling of CMOS. [ABSTRACT FROM AUTHOR]