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In this paper, for the first time, we study the impact of self-heating on the statistical variability of bulk and Silicon-on-insulator FinFETs designed to meet the requirements of the 14/16-nm technology node. The simulations are performed using the Gold Standard Simulations atomistic simulator GARAND using an enhanced electrothermal model that considers the impact of the fin geometry on the thermal conductivity. In the simulations, we have compared the statistical variability obtained from full-scale electrothermal simulations with the variability at uniform room temperature and at the maximum or average temperatures obtained in the electrothermal simulations. The combined effects of line edge roughness and metal gate granularity are considered. The distributions and the correlations between key figures of merit, including the threshold voltage, ON-current, subthreshold slope, and leakage current are presented and analyzed. [ABSTRACT FROM PUBLISHER]

In this paper we illustrate how the predictive Technology Computer Aided Design (TCAD) process device simulation can be used to evaluate process, statistical, and time-dependent variability at the early stage of the development of new technology. This is critically important for the delivery of accurate early Process Design Kits, including process variability, statistical variability, time-dependent variability (degradation) and their interactions and correlations. This is also critical to the TCAD-based Design-Technology Co-Optimisation (DTCO). To accomplish this task, the fast, large area Coventor virtual fabrication platform SEMulator3D was integrated in the GoldStandradSimulations TCAD-based DTCO tool chain. Published data for Intel 22-nm FinFET technology are used to illustrate and validate the results of the TCAD process and device simulation, the compact model extraction, and the statistical circuit simulation. [ABSTRACT FROM AUTHOR]

A comprehensive statistical investigation of the increase in resistance associated with charge trapping in atomistic simulations is presented. A wide range of doping densities and mesh spacing are considered for both classical and quantum formalisms. A doping-dependent correction factor to modify the mobility model for the atomistic simulations is proposed to suppress the error related to the fictitious charge trapping. The validity of the new mobility model is tested in the statistical simulations of the transistors corresponding to 20-nm bulk CMOS and 14-nm FinFET transistors. [ABSTRACT FROM AUTHOR]

In this paper, we study and compare Si versus Ge pMOS FinFETs at advanced node dimensions using ensemble Monte Carlo simulations. It is found that due to large external resistance, lack of stressing methods, smaller bandgap, larger dielectric constant, and increased variability that in the absence of major innovation, Ge is not an ideal candidate for channel replacement material of pMOS in future CMOS technology generation FinFETs. In order for Ge to compete with Si, it would at a minimum require a stressing mechanism and improved contact resistance, but leakage and variability would still be a concern for low-power applications. [ABSTRACT FROM AUTHOR]

A set of analytical models based on the Pearson distribution function applied to the modeling of ion implantations in the 3-D structure of FinFETs is presented. The method provides a succinct way to simulate the doping profiles in FinFETs at low computational cost. Compared to previous analytical methods based on Gaussian distributions, this approach handles more realistic asymmetrical doping distributions arising from ion implantation. A simulation module in C++ has been developed to model ion implantations in FinFETs based on this analytical approach. The simulation module is demonstrated in an example simulation of a silicon-on-insulator FinFET with physical gate length of 20 nm. [ABSTRACT FROM PUBLISHER]

This paper presents a comprehensive simulation study of the process and statistical variability in 16-nm technology node bulk and silicon-on-insulator (SOI) fin field effect transistors (FinFETs). The devices are carefully designed to offer good manufacturability while meeting the performance requirements of the 16-nm technology. First, the sensitivity of the two types of FinFETs to process- induced channel length, fin-width, and fin-height variability is carefully investigated and compared based on the threshold voltage, OFF-current, and overdrive current sensitivity. Possible improvement of the SOI substrate design for reduction of the SOI FinFET sensitivity to fin-width variation is also discussed. The individual and combined impact of the relevant statistical variability sources including random discrete dopants (RDDs), fin-line edge roughness, gate-line edge roughness, and metal gate granularity are studied and compared for the nominal 25-nm gate length FinFET designs. [ABSTRACT FROM PUBLISHER]

Current advanced transistor architectures, such as FinFETs and (stacked) nanowires and nanosheets, employ truly three-dimensional architectures. Already for aggressively scaled bulk transistors, both statistical and systematic process variations have critically influenced device and circuit performance. Three-dimensional device architectures make the control and optimization of the device geometries even more important, both in view of the nominal electrical performance to be achieved and its variations. In turn, it is essential to accurately simulate the device geometry and its impact on the device properties, including the effect caused by non-idealized processes which are subject to various kinds of systematic variations induced by process equipment. In this paper, the hierarchical simulation system developed in the SUPERAID7 project to study the impact of variations from equipment to circuit level is presented. The software system consists of a combination of existing commercial and newly developed tools. As the paper focuses on technological challenges, especially issues resulting from the structuring processes needed to generate the three-dimensional device architectures are discussed. The feasibility of a full simulation of the impact of relevant systematic and stochastic variations on advanced devices and circuits is demonstrated. [ABSTRACT FROM AUTHOR]