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A high-permittivity (high- ${k}$) inserted-oxide FinFET (iFinFET) structure with low-permittivity inner spacers is proposed for CMOS transistor scaling to the 3-nm technology node and beyond. The process to fabricate an iFinFET is similar to the process to fabricate a nanosheet field-effect transistor (NSFET); no additional lithography masks are needed. Unlike the NSFET and the nanowire field-effect transistor (NWFET), which each require significant spacing between the nanosheets or nanowires (NWs) to accommodate metallic gate and dielectric insulator multilayer stacks, the iFinFET requires only a single ultrathin high- ${k}$ inserted-oxide (i-oxide) layer between the NWs, allowing more NWs to be vertically stacked within the constraint of a maximum total channel height. The i-oxide layers serve to allow fringing electric fields from the gate to penetrate into the NWs to achieve improved electrostatic integrity. Simulated performance characteristics of the proposed iFinFET structure are compared against those for the FinFET, NWFET, and NSFET. The iFinFET is projected to achieve the best electrical performance when the footprint (device layout width) is less than 80 nm. [ABSTRACT FROM AUTHOR]

A scheme for precisely adjusting the drive strength of an inserted-oxide FinFET (iFinFET) comprising two nanowire (NW) channel regions that are separated by a thin oxide layer, to enhance the manufacturing yield of a minimally sized six-transistor static random access memory (6T-SRAM) cell, is investigated in this paper. The 3-D process simulations show that the upper NW channel region can be selectively rendered nonconducting by dopant ion implantation followed by thermal annealing so that its threshold voltage is greater than the supply voltage (${V}_{\text {DD}}$). Furthermore, the position of the inserted-oxide layer can be adjusted to balance the tradeoff between the read stability and write-ability to achieve the lowest minimum cell operating voltage (${V}_{\text {min}}$). Using a compact transistor model calibrated to 3-D device simulations, doped iFinFET technology is projected to enable ${V}_{\text {min}}$ of a minimally sized 6T-SRAM cell to be substantially lower than ${V}_{\text {DD}}$ , eliminating the need for write-assist circuitry and lowering power consumption. [ABSTRACT FROM AUTHOR]

The performance of a p-channel FinFET comprising a heterogeneous silicon (Si) and silicon-germanium (Si0.9Ge0.1) channel region is evaluated using three-dimensional TCAD simulations and benchmarked against a conventional p-channel Si FinFET. The results show that the hetero-channel design provides for larger ON-state current while maintaining comparable electrostatic integrity as the conventional design due to the valence band offset between Si0.9Ge0.1 and Si. The enhanced performance is achieved with a relatively low Ge mole fraction (10%) in the channel region for ease of manufacture. Therefore, the hetero-channel FinFET is promising for future low-power applications. [ABSTRACT FROM AUTHOR]

A hybrid fin/planar lateral double-diffused MOSFET (LDMOS) design (hybrid FET) is proposed for the high-voltage input–output devices in a FinFET-based system-on-chip (SoC) technology. 3-D technology computer-aided design simulations show that a planar drift region and a planar drain region are advantageous for higher breakdown voltage (BV) to specific on-state resistance ( R\text {on\_{}$sp}}) ratio (BV2/ R\text on\sp}) . By slightly extending the planar portion of the semiconductor active region into the gated channel region, the theoretical limit of BV2/ R\text {on\_{}$sp}}$ for LDMOS can be surpassed. Hybrid FETs can be fabricated using a process flow that is compatible with the state-of-art FinFET SoC technology. [ABSTRACT FROM PUBLISHER]

A scheme for controllably adjusting transistor drive strength in inserted-oxide FinFET (iFinFET) technology is proposed, to enable cell ratio tuning for a minimally sized six-transistor (6T) SRAM cell. Specifically, one or more of the stacked nanowire channels within an iFinFET can be made to be essentially non-conducting by ion implantation to increase its threshold voltage. Via 3-D device simulations and a calibrated compact $I$ – V$ model, this scheme is projected to enable more than 0.1 V reduction in minimum cell operating voltage ( V_{\mathrm {MIN}}) for a 6T SRAM high-density cell design. [ABSTRACT FROM PUBLISHER]