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In wafer dicing operations, several chipping effects involving breakage or micro-cracks were often observed along the cut line of the glass interposer, mainly due to its brittle and hard material characteristics. When the interposer is further subjected to thermal loading in the subsequent packaging process and environmental stressing conditions, these micro-cracks or breakages may continue to grow or propagate throughout the interposer until the structure ruptures, leading to reliability issues. To seek a resolution of the reliability enhancement, a better and clearer comprehension of the fracture physics and mechanisms is crucial. Thus, the study aims at investigating the fracture behaviors of glass interposers, provided by a local leading carrier supplier, under an accelerated thermal cycling (ATC) condition through numerical simulation and experimental testing. Focus is placed on the influences of the ATC loading on the mode I fracture toughness or stress intensity factor of the glass interposers, and more importantly, a design guideline is provided for improved fracture resistance or reliability. The study starts by evaluating the ultimate strength and critical fracture toughness of various glasses used in the interposer. In the thermal-mechanical numerical analysis, a 2D plane strain finite element analysis (FEA) technique is proposed. The proposed technique is benchmarked with the widely applied local fine mesh global simulation. Furthermore, to conduct fracture analysis, the virtual crack closure technique incorporating the degenerated element is employed. The calculated results are compared with each other and with the critical fracture toughness obtained from the experiments. At last, through parametric computational analysis, the geometry and material parameters most affecting the fracture behaviors are identified, and the optimal combinatorial design of these parameters is obtained. [Display omitted] • A methodology for fracture strength in glass interposers with dielectric coatings for dicing. • A deviation of fracture toughness between FEM and the theoretical solution was 4.3 %. • Factors involving crack length, interfacial crack effects, dielectric's elastic modulus. • Temperature effect is considered in the condition of crack length. • The interfacial crack length has the risk between glass and dielectric, when smaller than 40 μm. [ABSTRACT FROM AUTHOR]

Managing the stability of related processes in the integrated manufacturing of three-dimensional integrated circuits (3D-ICs) remains unresolved, especially with regard to the thermo-mechanical behavior of copper filled through silicon via (TSV) interposer during annealing. In this work, transient annealing is successfully applied on the filled copper using only one form of selective heating technology. To address the integration problem, transient thermo-structural coupling analysis using a nonlinear finite element simulation is proposed. Compared with the experimental data, the proposed simulation is found to be highly reliable. Analytical results show that temperature decreases from the top surface of the TSV to other regions within a silicon-based TSV interposer. Stress-induced fracture is common among bonded films, thereby worsening the subsequent mechanical reliability of 3D-IC devices. Moreover, the extent of keep-out zone induced by residual stress of Cu-filled TSV is also defined through the simulation-based mobility gain of nano-scaled devices. In accordance with the results of this investigation, an improvement can be obtained by optimizing the fabrication parameters during annealing. The proposed technology provides a high throughput and reliable processes in TSV manufacturing. [ABSTRACT FROM AUTHOR]

Abstract: This study demonstrated that advanced strained engineering in contact etching stop layer (CESL) combined with silicon germanium (Si1−xGex) stressors can be efficiently utilized to enhance the performance of devices. Lattice mismatch stress was induced to establish an Si1−xGex channel integrated with intrinsic stress of CESL, which consists of multiple stressors, to analyze the stress contour of the concerned channel in n-type metal–oxide–semiconductor field effect transistors (nMOSFETs) by three-dimensional (3D) finite element analysis (FEA). The types of intrinsic CESL stress considered in this study were tensile (1.1GPa) (t-CESL) and compressive (−2.0GPa) (c-CESL). Germanium mole fractions, including 0%, 22.5%, and 25%, utilized in the Si1−xGex channel were selected to carefully analyze their impact on the Si1−xGex channel. The effect of channel geometries, which are composed of aspect ratio of length and width, was considered as well. Results reveal that the stress components of the Si1−xGex channel increases significantly when the amount of Si1−xGex layer increases. A change in the length and width of the channel induces inversion in the Si1−xGex channel regarding stress conventions in the direction of the channel's length and width. Results predicted by the proposed FEA were consistent with experimental data as validated by the nMOSFET with an Si0.775Ge0.225 channel. Comparison of the simulation results of FEA with two-dimensional (2D) and 3D models was performed. The results show that wide gate width in the 3D model can induce a response to the calculated results similar to that obtained in a 2D situation. [Copyright &y& Elsevier]

Abstract: The adoption of shallow trench isolation (STI) integrated with a contact etching stop layer (CESL) is regarded as an important technique in strain engineering that significantly boosts transistor mobility of nanoscale devices because the node technology of the metal-oxide-semiconductor field-effect transistor (MOSFET) is continually scaled down to 22nm and lower. A finite element method based on stress simulation is implemented in this research to investigate the effects of STI geometric profiles on n-type MOSFET performance. The mechanism for transferring STI and CESL intrinsic stresses under the aforementioned conditions to the silicon (Si) channel is explained by considering the major procedures of process-induced stress. Results indicate that the approaches of suitable sunken STI patterns are more useful than those of a flat STI prototype because a difference in the resultant stress distribution for the Si channel region is introduced by the device profiles. The piezoresistance effect of Si is being actively explored at present to improve the characteristic of transistors because this effect has been extensively used in mechanical stress technology. A crystal strain resulting in a change in electrical conductivity is observed because of the aforementioned piezoresistance effect. Induced mobility gains from STI and CESL stressors are systematically observed. Integrating a tensile CESL and an STI stressor region results in almost 10% to 20% enhancement in carrier mobility. [Copyright &y& Elsevier]

Abstract: The layout patterns of nano-scale devices have significant impacts on device performance when an increase in operating velocity is considered. Thus, advanced strain engineering of metal-oxide-semiconductor field-effect transistors (MOSFETs) is necessary when highly scaled gate lengths are employed. The foregoing mechanical effects are observable when a device with a narrow channel width is utilized. However, when a device integrated with an extended poly gate is scaled down to several hundreds of nanometers, the induced stress contours of the channel region and corresponding mobility gain become troublesome and must be resolved. This study investigates the mechanical impacts of extended gate widths on the mobility gains of p-type MOSFETs. The selected MOSFET has a SiGe stressor embedded in its source and drain regions, as well as a compressive contact etch stop layer. Three-dimensional finite element simulation is performed to emulate the stress contour within the Si channel and estimate the related mobility gain. Sensitivity analyses of the simulation results using factorial designs and response surface methodology indicate that stresses within the Si channel are induced by a bending force determined by the extension of the poly width. A significant enhancement in mobility gain is found when an extended poly width combined with proper arrangements of the device geometry is applied. [Copyright &y& Elsevier]

Abstract: Developing a robust predicting methodology on the interfacial fracture energy of dissimilar materials is urgently needed to meet the mechanical strength requirements for investigating novel materials and subsequent device structures with the bonded types of multi thin films. Thus, this paper provides an overview of useful approaches according to linear-elastic interfacial fracture mechanics, such as J-integral method, modified virtual crack closure technique (MVCCT), and analytical solutions derived from the relationship between the stress field of delaminated tip and crack tip opening displacements to compare their estimated capability of cracking energy. A popular technique for determining the interface adhesion of thin coatings is the four-point bending test (4-PBT). The testing vehicles of 4-PBT allow a more thorough validation of the foregoing predicted approaches based on finite element analysis compared with the simulated results with related experimental data. The critical energies of 18J/m2, 78.53J/m2, 52.01J/m2, and 71.02J/m2 for the bonded interfaces of SiO2/SiLK, Ta/SiLK, TaN/SiLK, and Si3N4/SiLK stacked nano-scaled thin films are precisely judged, respectively. The predicted results of the J-integral method match well with the MVCCT estimation. The results reveal that the opening fractured mode is dominant at the beginning of the crack advances along the bonded interface of Ta/SiLK, TaN/SiLK, and Si3N4/SiLK stacked films as the interfacial crack length increases. Moreover, the essential trends of dependences for the modulus ratio and thickness ratio of stacked thin films on interfacial energy release rate are logically identified and investigated. Therefore, this paper could be regarded as a design guideline of interfacial fracture behavior for stacked films utilized in the development of advanced device technologies. [Copyright &y& Elsevier]

Abstract: The integration of thin film technology into the fabrication of semiconductor transistors has given rise to significant challenges in the design of multi-level back-end-of-line interconnects. The interfacial adhesion between Al metal and TiN barrier is one of the major factors that affect interconnect reliability. Analyzing the effect of the interconnect structures of Al/TiN barriers on interfacial cracking energy under flexural loading is an interesting research direction. This work proposes a robust estimation of interfacial cracks by simulation-based methods to satisfy the mechanical design requirements for multi-level interconnect systems. A constant bending moment can be generated with the framework of the four-point bending test (4-PBT). A 4-PBT simulation model can be used in finite element analysis, combined with the J-integral method and the modified virtual crack closure technique, to accurately predict the interfacial fracture energy of Al/TiN films. Preliminary results indicate a considerable increase in energy release rate. Energy is released as a crack along the interface of the Al/TiN films passes through the region above the parallel metal lines of patterned interconnects, especially for a Cu/SiLK material system. The results also show that dielectrics can serve as stress buffer layers that inhibit crack growth. [Copyright &y& Elsevier]

Abstract: Organic electronic devices with multi-stacked thin films based on polymeric substrates are proposed for use in mainstream flexible organic light-emitting diode displays. To achieve the above-mentioned requirements, indium tin oxide (ITO) thin film, a brittle, inorganic material, is necessary to be utilized as a transparent electrode in flexible electronics. The failure rate of ITO films is of concern when introducing harsh flexural load in terms of reliability. This study utilizes a simulation-based factorial-design approach to determine a suitable combination of mechanical characteristics of ITO film stacked with other films to reduce the neutral plane (NP) impact of stacked films. The results indicate that both Young's modulus and cover plate thickness are major factors that alter the stress magnitude of ITO films. Moreover, the simulated results for stacked structures reveal that the distance between the ITO film and NP is significantly reduced when polyimide materials, rather than steel metal, are used for the cover plate. In the meanwhile, ITO film stress drops in virtue of lower mechanical stiffness and lesser thickness direction between the NP and ITO films in a multi-stacked film structure. [Copyright &y& Elsevier]

Abstract: The interfacial adhesion of thin films between Al metal and TiN barrier is one of the major concerns dominating the mechanical reliability of semiconductor devices. The measured accuracy of cracking energy for stacked films with a nanoscale order is arduous to preserve because of the uncertainty in specimen preparations and instrumental operations. Consequently, the present research proposes a robust estimation of interfacial cracks using simulation-based methodologies to meet the requirement for mechanical designs in multi-level interconnected systems of electronic devices. According to the framework of the four-point bending test (4-PBT), the interfacial fracture energy of Al/TiN films is predicted via finite element analysis (FEA), combined with the J-integral method and modified virtual crack closure technique (VCCT). The foregoing simulated approaches are also verified by related analytical solutions and experimental data. Moreover, the effects of several patterned types of metal lines underneath the Al/TiN interface with various embedded cracks are analyzed. The primary results highlight a significant increase in the energy release rate (G) induced by the passing of a crack along the interface of Al/TiN films through the region below a metal line with a high degree of hardness. Dielectrics with a lower modulus would have the capacity to restrain progressive crack growth. Thus, a high G is expected to drop, as simultaneously demonstrated by the present simulated methodologies. [Copyright &y& Elsevier]

3-D integration provides a promising approach for the construction of complex microsystems through the bonding and interconnection of individually optimized device layers without sacrificing system performance. The use of traditional underfill processes is expected to face an arduous challenge as the filled gap of a large-scale chip is narrowed down to several micrometers. Consequently, the subsequent reliability of microbumps (\mu-bumps) joints and the relative assembly compatibility of stacked chips of 3-D IC packages deteriorate. To resolve this critical issue, a novel technology for wafer-level underfill film (WLUF) is developed. This paper demonstrates the steps that the proposed technology would take. These steps include the alignment of the WLUF-coated chip to the substrate chip and the elimination of voids to make the proposed technology work. However, the coplanarity of stacked thin chips after assembling with the WLUF, is an urgent problem that needs to be understood in detail. Therefore, this paper presents a nonlinear finite element analysis (FEA) using a process-oriented simulation technique to estimate the warpage of stacked thin chips. For experimental validation, the effects of several key designed factors on the thermomechanical behavior of chip-on-chip package under various bonding forces are investigated. The analytic results indicate that a chip thickness of <50∼\mum at the outermost region of the packaging structure without \mu-bumps significantly reduces approximately 2 \mum of gap between chips. This phenomenon is attributed to the major structural support at the purlieus of the chip via WLUF, which is extremely weak when a uniform bonding pressure is loaded. In addition, the subsequent cooling procedure of the WLUF further aggravates the warpage magnitude of the stacked thin chips. The results of this paper could serve as a guideline for further improvement of the bonding reliability and for the design of the structural optimization of packaging assemblies via the WLUF. [ABSTRACT FROM AUTHOR]