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\Al2\O3 high- \kappa stack is a strong candidate as the dielectric layer in Flash memory cells for technology generations beyond sub-20 nm. In this paper, the cause of abnormal VTH/VFB shift at low operating electric fields is investigated, i.e., VTH/VFB reduces at low positive gate biases and increases at low negative gate biases. It is found that this instability does not originate from the electrons trapping/detrapping from the gate nor from the dielectric relaxation. For the first time, extensive experimental evidences show that this shift is caused by as-grown mobile charges in \Al2\O3 layers generated by postdeposition annealing at 1000 ^\circ\C or above. Its impacts on program/erase windows and read/pass disturbance in Flash memory cells are also evaluated. [ABSTRACT FROM PUBLISHER]

High density of electron trapping in high- \kappa intergate dielectric (IGD) materials remains a major concern for planar memory cells with either poly-Si or hybrid floating gates (FGs). In this paper, for the first time, using the ultrafast I{-}V measurements, it is demonstrated that a significant portion of the P/E windows are actually contributed by electrons trapped initially in the high- \kappa$ IGD stacks during program/erase, and then discharged to FG or control gate during verification. More importantly, it is demonstrated, for the first time, that this fast charge transition can be suppressed using novel multilayer high- $\kappa$ IGD structures, and the fast window instability can be eliminated. [ABSTRACT FROM PUBLISHER]

Poly-Si (p-Si) channel used in 3-D Flash memory devices is the main source of degraded performance, such as the high interface state density. Charge pumping (CP) signals in the 3-D nanoscale vertical device with p-Si channel are analyzed in this paper using the variable amplitude CP technique. For the first time, it has been demonstrated experimentally that the broad CP edge is due to the threshold voltage variation in the p-Si channel caused by both the trapping in interface states and the source/drain p-n junction diffusion, and their impacts can be separately evaluated. Hot carrier stress in the tunneling FET operation modes and statistical analysis are used to provide supporting evidence. [ABSTRACT FROM PUBLISHER]

High-\kappa stacks have been used in the 20-nm generation of floating gate (FG) flash memory cells as the interpoly dielectric (IPD). However, electron trapping in high-\kappa materials remains a major concern for the further development of FG technology. For conventional FG cells, read/pass disturbance in the erased states is a major issue. In this paper, for the first time, it is observed that electron trapping/detrapping in the high-\kappa IPD layers can cause severe abnormal read/pass disturbances in the programmed states. Extensive evidence shows that this instability in programmed states originates from several competing mechanisms, including the redistribution of electron trapping between the IPD and FG and the electron discharging from FG/IPD into the control gate. This issue should be addressed in the development of future generations of FG Flash technology with higher-\kappa IPD materials. [ABSTRACT FROM PUBLISHER]

Endurance is one of the key criteria for Flash memory technologies, particularly for the generations beyond 30 nm with high-\kappa materials. It is observed in this paper that the electron trapping in high-\kappa layers causes threshold-voltage window closure under dynamic program/erase cycling operations. This closure does not originate from the generation of new traps or from further trapping of electrons injected from the gate during erasing. By utilizing a recently developed multipulse technique, it is found that the energy distribution of the electron trapping in the high-\kappa layer significantly changes after cycling. Electron trapping at the deeper energy levels continuously increases as cycling proceeds, because it does not reach saturation within one programming pulse. The trapping in deep levels cannot be discharged under typical erase conditions, and an increase in deep-level trapping also causes a reduction of trapping at shallow levels. It is concluded that the window closure observed in this paper is caused by a combination of increased deep trapping after erasing and a reduction of shallow trapping after programming. [ABSTRACT FROM PUBLISHER]

A new discharge-based multipulse technique has been developed in this paper, which overcomes the shortcomings of the existing techniques, such as the charge pumping, charge injection and sensing, and two-pulse C–V techniques. It captures the energy signature for electron traps across high- \kappa materials and can be a useful tool for material selection during technology development. Trap distributions in \HfO2, \Al2\O3, and HfAlO have been compared to identify the effects of material variation. It is observed that hafnium gives the shallow traps at about 0.45 eV above the silicon conduction band bottom (Si ECB), and the deep traps at 0.8 eV below the Si ECB are caused by aluminum. HfAlO combines the features in \HfO2 and \Al2\O3. A peak near the Si ECB has been observed in all the three materials. [ABSTRACT FROM PUBLISHER]