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This paper presents a partially pixel-parallel digital readout integrated circuit that overcomes the limitation of achievable digital resolution seen in megapixel-format infrared digital focal plane arrays (IR-DFPAs). It incorporates 5-bit in-pixel pulse frequency modulation (PFM)-based charge-to-digital converters and 10-bit successive approximation register (SAR) column analog-to-digital converters (ADCs). To increase the readout resolution, the residue charge at the end of the integration phase is fine converted to a 10-bit digital word and combined with the in-pixel data. This method is a compromise between fully pixel-parallel and fully column-parallel conversion approaches and favors the ever-growing trend toward small pitch FPAs by allowing a compact pixel size. A prototype consisting of a $32\times32$ array of pixels, 32 column SAR ADCs, and a timing controller block is designed and fabricated in a 90-nm bulk CMOS process. A modified version of the conventional PFM-based pixel is designed to help hold the residue charge. The design is targeted at medium-wave IR-DFPAs with frame rates up to 400 Hz. A signal-to-noise ratio of 79 dB is achieved with a full-well capacity of 2.4 Me-. [ABSTRACT FROM AUTHOR]

This journal presents a new high dynamic range ROIC with smart pixel which consists of two pre-amplifiers that are controlled by a circuit inside the pixel. Each pixel automatically decides which pre-amplifier is used according to the incoming illumination level. Instead of using single pre-amplifier, two input pre-amplifiers, which are optimized for different signal levels, are placed inside each pixel. The smart circuit mechanism, which decides the best input circuit according to the incoming light level, is also designed for each pixel. In short, an individual pixel has the ability to select the best input amplifier circuit that performs the best/highest SNR for the incoming signal level. A 32 × 32 ROIC prototype chip is designed to demonstrate the concept in 0.18 μ m CMOS technology. The prototype is optimized for NIR and SWIR bands. Instead of a detector, process variation optimized current sources are placed inside the ROIC. The chip achieves minimum 8.6 e - input referred noise and 98.9 dB dynamic range. It has the highest dynamic range in the literature in terms of analog ROICs for SWIR band. It is operating in room temperature and power consumption is 2.8 μ W per pixel. [ABSTRACT FROM AUTHOR]

This paper presents a digital readout integrated circuit (DROIC) implementing time delay and integration (TDI) for scanning type infrared focal plane arrays (IRFPAs) with a charge handling capacity of 44.8 Me − while achieving quantization noise of 198 e − and power consumption of 14.35 mW. Conventional pulse frequency modulation (PFM) method is supported by a single slope ramp ADC technique to have a very low quantization noise together with a low power consumption. The proposed digital TDI ROIC converts the photocurrent into digital domain in two phases; in the first phase, most significant bits (MSBs) are generated by the conventional PFM technique in the charge domain, while in the second phase least significant bits (LSBs) are generated by a single slope ramp ADC in the time domain. A 90 × 8 prototype has been fabricated and verified, showing a significantly improved signal-to-noise ratio (SNR) of 51 dB for low illumination levels (280,000 collected electrons), which is attributed to the TDI implementation method and very low quantization noise due to the single slope ADC implemented for LSBs. Proposed digital TDI ROIC proves the benefit of digital readouts for scanning arrays enabling smaller pixel pitches, better SNR for the low illumination levels and lower power consumption compared to analog TDI readouts for scanning arrays. [ABSTRACT FROM AUTHOR]

This paper presents a design and analytical approach to significantly reduce the dynamic power consumption of front-end pixel design for digital readout integrated circuits (DROICs) in digital pixel sensor (DPS) arrays. DPS architecture relies on coarse quantization with pulse frequency modulation (PFM) and a novel approach of extended integration incorporated to achieve lower noise. The design is fabricated in 90 nm CMOS process with pixel pitch of 30 µm. Proposed architecture can attain eminently high charge handling capacity of 2.2Ge- with a quantization noise of 1072e- and extremely low power dissipation of 14.28 mW. The proposed dynamic power reduction paradigm enables to alleviate the overall power consumption to 35% as compared to state-of- art PFM based 256×256 DPS array with the lowest Figure of Merit (FoM) of 297fJ/LSB reported earlier. The power reduction escalates further for higher detector currents and large format Focal Plane Arrays (FPA). The proposed design is tested and compared to our previous DROIC measurement results and other works in terms of power and quantization noise. [ABSTRACT FROM AUTHOR]