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A Doppler radar operating as a Phase-Locked-Loop (PLL) in frequency demodulator configuration is presented and discussed. The proposed radar presents a unique architecture, using a single channel mixer, and allows to detect contactless vital signs parameters while solving the null point issue and without requiring the small angle approximation condition. Spectral analysis, simulations, and experimental results are presented and detailed to demonstrate the feasibility and the operational principle of the proposed radar architecture. [ABSTRACT FROM PUBLISHER]

A 1.3 nJ/b IEEE 802.11ah TX for IoT applications is presented. A fully-digital polar architecture consisting of an all-digital PLL-based frequency modulator and an AM-retiming $\Delta \Sigma $ switched-capacitor PA (SC-PA) achieves more than $10\times $ power reduction than state-of-the-art OFDM TXs. Several circuit-design techniques such as LSB truncation error feedback are proposed to efficiently pre-process the AM/PM data to improve the TX performance. A design approach of the SC-PA for optimum overall efficiency is introduced. The PLL spur level is reduced to 55 dBc by a switched-capacitor based digital-to-time converter. A dynamic divider is implemented together with a 1.8 GHz oscillator for efficient LO generation. Fabricated in a 40 nm CMOS process, this TX fulfills all the IEEE 802.11ah mandatory-mode PHY requirements with 4.4% EVM and > 4.8 dB spectral mask margin, while consuming 7.1 mW from a 1 V supply when delivering 0 dBm output power. [ABSTRACT FROM AUTHOR]

This article discusses the radio system requirements and design trade-offs of a low-power 2.3/2.4 GHz IEEE 802.15.6-narrowband transmitter for body area network applications. The IEEE 802.15.6 narrowband PHY adopts nonconstant envelope DPSK modulations. Transmitter architecture selection is a major challenge because it needs to provide both amplitude and phase modulation, with good efficiency and strict requirements on modulation accuracy and linearity for non-constant envelope modulations. A PLL-based polar transmitter with a Sigma-Delta digitally controlled power amplifier (SD-DPA) is employed for its excellent energy efficiency. Finally, this article discusses the circuit design considerations and implementation results. With balance between analog and digital implementation, and careful planning of the radio system, the polar transmitter presented in this article can meet all of the specifications defined in IEEE 802.15.6 with abundant margin, while having extremely low power consumption of 5.4 mW and excellent energy efficiency of 5.4 nJ/bit. [ABSTRACT FROM PUBLISHER]