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Modern wideband receivers need to operate linearly in the presence of strong out-of-band blockers. In this article, we introduce a blocker-tolerant harmonic rejection (HR) receiver, which can suppress blockers at the local oscillator harmonics. The suppression is achieved by applying the HR in two stages, such that the first HR already occurs at the first gain-stage output. The proposed receiver achieves this HR with a simple six-phase local-oscillator (LO) clocking. The proposed design also uses simple gain coefficients of ±1 while implementing HR in two stages that compensates for the mismatch effects of each stage. In addition, the near-band blocker linearity is improved by implementing a third-order baseband feedback response, which acts in conjunction with the $N$ -path filtering. Implemented in a 28-nm Fully-Depleted Silicon-on-Insulator (FDSOI) process, the receiver demonstrates the 18–37-dB HR from the first stage and 46–53 dB of HR in total. Furthermore, a blocker compression point (BCP) of 2.5 dBm for a third harmonic blocker and a near-band BCP of −6.5 dBm are achieved. [ABSTRACT FROM AUTHOR]

This paper presents a wideband direct ΔΣ receiver for the 0.7–2.7 GHz frequency range. The architecture embeds a wideband direct-conversion RF front-end into a continuous-time feedback ΔΣ modulator, which initiates the analog-to-digital conversion of the selected channel already at the RF nodes. A feedback-type architecture enables simultaneous filtering of nearby interfering signals. The inductorless 40 nm CMOS receiver supports programmable ΔΣ modulator coefficients and RF channel bandwidths up to 20 MHz. The receiver consumes 90 mW from a 1.1 V supply, and it provides a peak SNDR of 46 dB, NF of 5.9–8.8 dB, and an IIP3 of -2 dBm. [ABSTRACT FROM AUTHOR]

This paper presents the analysis, design, and measurements of a 2.5-GHz receiver front-end in a 40-nm CMOS technology. The front-end utilizes RLC-resonator quality factor (Q) boosting and four-phase N-path filtering to improve the blocker filtering capabilities of the low-noise amplifier (LNA). Systematic analysis is performed in order to obtain a thorough design approach. Particular attention is paid to the passive mixer switches in the RLC case, for which we show that minimum switch resistance does not provide best noise figure (NF), nor best relative blocker attenuation. Moreover, the N-path filter extends the stable operating region of a Q-boosted LNA, and adding a noisy Q-boosting circuit can actually improve the receiver NF in practical realizations. The experimental CMOS front-end is flip-chip packaged, and a parasitic-aware input matching method for the electrostatic-discharge-protected LNA is proposed, analyzed, and verified. In nominal operation, the programmable front-end achieves a measured gain of 39 dB, an NF of 3.5 dB, and an out-of-band input-referred third order intercept point of >\0 dBm, while consuming 48 mA from a 1.1-V supply. [ABSTRACT FROM AUTHOR]

This brief analyzes the dual role and operation of the low noise amplifier (LNA) in the recently introduced direct delta–sigma receiver (DDSR). First, the LNA functions as a transconductor in an integrator stage, and in this role, we explore the effects of LNA output impedance on quantization noise shaping by the system. In the second role of a voltage preamplifier, we show how the closed-loop DDSR structure impacts LNA voltage gain and system noise. LNA and system properties are thus intertwined and lead to the need for careful codesign. The reliability of the utilized continuous-time DDSR approximation is verified by simulating a sample receiver model. [ABSTRACT FROM AUTHOR]