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Herein, the electrical and thermal performance of lateral AlGaN/GaN high electron mobility transistors (HEMTs) and metal‐insulator‐semiconductor field effect transistors (MISFETs) fabricated with 11 μm thick GaN buffer layers on 200 mm diameter Qromis Substrate Technology (QST) substrates are investigated. The QST substrate has a polycrystalline core engineered to be coefficient of thermal expansion (CTE)‐matched to GaN to minimize wafer bow and residual stress in the GaN film as a result of epitaxial growth. Raman spectroscopy is used to determine the biaxial residual stress in the GaN buffer of the as‐fabricated devices. Electrical characterization is demonstrated on the HEMTs including DC and pulsed output characteristics, DC transfer characteristics, Hall mobility, carrier concentration, sheet resistance, median transition frequency, and maximum stable gain. Finally, the thermal performance of the AlGaN/GaN MISFET is assessed via thermoreflectance thermal imaging at DC power densities up to 19 W mm−1. The thermal resistance of the MISFET, calculated using the peak temperature rises on the gate electrode for DC power densities <10 W mm−1, is measured to be 15.4 mm K W−1, which is comparable with state‐of‐the‐art GaN‐on‐Si lateral transistors. [ABSTRACT FROM AUTHOR]

A high‐voltage AlN/GaN superlattice (SL) buffer for monolithic AlGaN/GaN power circuits is experimentally compared with a step‐graded AlGaN/GaN buffer. The SL as part of a 5.1 μm epitaxial stack withstands over 1.3 kV. Although the step‐graded buffer is sufficient for low‐side circuits, the operation voltage of monolithic topologies such as a half‐bridge is limited: static negative back gating at −200 V depletes the lateral channel completely. Asymmetrical buffer leakage at a positive substrate voltage of +250 V limits the operation voltage further. The SL buffer mitigates both effects: a negative substrate voltage of −200 V reduced the lateral channel current only by 25%. However, this condition is not required for half‐bridge operation on the SL, because low symmetrical vertical buffer leakage at substrate voltages of ±500 V allows operation of power topologies with positive substrate bias. High‐electron‐mobility transistors (HEMTs) on the graded buffer show excessive threshold voltage shift at negative substrate bias. On the SL buffer, the threshold voltage is shifted only +1 V from negative substrate biases, which allows monolithic high‐voltage power topology operation. 98.8% efficient operation of a 6 × 4 mm2 GaN‐on‐Si power integrated circuit with a monolithic half bridge, freewheeling diodes, and drivers is demonstrated on the SL. [ABSTRACT FROM AUTHOR]

Tomorrow's power electronic systems require cost‐saving and more efficient power conversion solutions. The heterogeneous integration of GaN‐based high electron mobility transistors (HEMTs) together with silicon CMOS by micro‐Transfer‐Printing could be a key technology for this. It enables the integration of highly integrated mature CMOS logic functionality with fast GaN HEMT output drivers with very low on‐state and switching losses. The scalability by design measures of the printed HEMT is investigated in terms of drain‐to‐gate spacing and channel width defining breakdown voltage and area‐related parameters like on‐resistance. The design flexibility of the micro‐Transfer‐Printing by printing the HEMTs on top of the CMOS devices without restrictive design rule limits is investigated by CMOS DC parameter comparison and thermal TCAD Design Of Experiment (DOE) study. No electrical or thermal functional limitation of printing the HEMTs directly on top of the CMOS dielectric layer stack was found. This enables the usage of the isolation capabilities of the CMOS dielectric layer stack to enhance the HEMT breakdown voltage. [ABSTRACT FROM AUTHOR]