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The threshold voltage (VTH) of an enhancement-mode Schottky-type p-GaN gate high-electron-mobility transistor (HEMT) is found to have a special dependence on the drain bias. The device commonly requires higher gate voltage to switch on the transistor from a high-drain-voltage off-state than what is expected from the static device characteristics. The reason behind the dynamic VTH has been proved to be the floating p-GaN layer, where charges could be stored and further influence VTH under different drain bias. In this article, a SPICE-compatible equivalent circuit model is presented according to the structure of Schottky-type p-GaN gate HEMTs. It features a floating node to imitate the charge storage process within the gate stack. Compared to conventional models, the proposed model could accurately predict the dynamic VTH characteristics and switching behaviors of power electronics circuits, where Schottky-type p-GaN gate HEMTs are deployed as power transistors. The phenomena related to the dynamic VTH, including the disappearance of Miller plateau, the overestimated false-turn-on problem, and the higher reverse conduction loss are evaluated with a half-bridge circuit and the merits of the proposed model are verified. [ABSTRACT FROM AUTHOR]

By deploying a surface reinforcement layer (SRL) at the interface between Schottky metal and ${p}$ -GaN in the gate stack, a ${p}$ -GaN gate high-electron-mobility transistor (HEMT) with enhanced gate reliability is demonstrated. Prior to the gate metal deposition, the SRL is formed by an oxygen-plasma treatment and a subsequent high-temperature annealing process (at 800 °C) that enables surface reconstruction. Such a process converts several nanometers of ${p}$ -GaN near the surface into a crystalline GaON layer, which exhibits stronger immunity to hot electron bombardment. With nearly identical threshold voltage and ON -resistance, the ${p}$ -GaN gate HEMT with SRL yields two orders of magnitude reduction in gate leakage current at ON -state and an increase from 10.5 V to 12.7 V in forward gate breakdown voltage. Time-dependent gate breakdown measurement reveals an increase from 5.9 V to 7.8 V in the maximum ON -state gate drive voltage for a 10-year lifetime with a 1 % gate failure rate, which effectively expands the operating voltage margin of the ${p}$ -GaN gate power HEMT. [ABSTRACT FROM AUTHOR]

The impacts of static and dynamic gate stress on the threshold voltage (${V}_{\text {TH}}$) instability in Schottky-type ${p}$ -GaN gate AlGaN/GaN heterojunction field-effect transistors are experimentally investigated. ${V}_{\text {TH}}$ shifts negatively under large positive bias static stress (${V}_{\text {G}}\_ {\text {stress}} > 5$ V) by adopting conventional quasi-static characterization techniques. In contrast, ${V}_{\text {TH}}$ under fast-dynamic-stress exhibits positive shift, and a positive frequency dependence occurs within a wide range of frequency from 10 Hz to 1 MHz. The different ${V}_{\text {TH}}$ instability behavior under static and dynamic stress mainly originates from the time-dependent charges (electrons and holes) storage/release mechanisms in the ${p}$ -GaN layer, which is floating in the Schottky-type ${p}$ -GaN gate HEMT. [ABSTRACT FROM AUTHOR]

Under reverse-bias stress (i.e., OFF-state stress with ${V} _{\text {GS}} < {V}_{\text {TH}}$) with high drain voltage, ultraviolet (UV) illumination and larger negative gate bias are found to accelerate the positive shift in threshold voltage (${V}_{\text {TH}}$) of enhancement-mode GaN MIS-FETs with fully recessed gate. These results suggest a hole-induced degradation mechanism. In the absence of UV illumination, holes could be generated by impact ionization in the high electric-field region, which is initiated by electrons injected from the source through the buffer layer. With a larger negative gate bias, more holes will flow to the gate side and pass through the silicon nitride (SiNx) gate dielectric, as SiNx does not present any energy barrier to holes. The enhanced hole transport through the dielectric under large negative gate bias could accelerate new defects generation and therefore result in the larger positive threshold voltage shifts. [ABSTRACT FROM AUTHOR]

In this paper, we carried out a systematic comparison between the enhancement-mode GaN-based fully recessed metal-insulator-semiconductor field-effect transistors (MIS-FETs) and partially recessed MIS-high-electron-mobility transistors (MIS-HEMTs) with the same gate dielectric stack (LPCVD-SiNx/PECVD-SiNx) that has delivered promising long-term reliability and stability. Despite a moderately larger on-resistance (${R}_{ \mathrm{ON}}$), the MIS-FETs deliver superior ${V}_{\text {TH}}$ uniformity and thermal stability. Under long-term gate bias stress, both the MIS-HEMT and MIS-FET deliver similar small positive-bias temperature instability, while the negative-bias temperature instability of the MIS-HEMT is much larger than that of MIS-FET. The MIS-FET also delivers a higher ${V}_{\text {TH}}$ stability than the MIS-HEMT under dynamic gate bias stress. It is suggested that the differences in ${V}_{\text {TH}}$ stability mainly originate from the different spatial separation between the trap states and the conducting channel, with it being larger in MIS-HEMT than in MIS-FET. [ABSTRACT FROM AUTHOR]