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Architectures for the memory address calculation unit of a holographic memory device have been deeply analyzed in the literature. Finite-precision analysis and the selection of parameters to ensure a discrepancy between the hologram plane and the observation plane of less than 1% has been performed by other designers. However, a fault-tolerant architecture implemented on field-programmable gate array (FPGA) for an Optically Reconfigurable Gate Array has not been proposed yet. Due to the importance of this unit in environments with high levels of radiation, such as robots in nuclear disasters or satellites in space, which are the most common applications, there is a real interest in protecting this hardware. This work introduces two main contributions: i) replaces the calculation of distances through a Coordinate Rotation Digital Computer (CORDIC) unit in order to save area and ii) improves the ratio of fault-detection and extends the input range of the trigonometric computations to exploit more efficient error detection techniques. The derived architecture allows us to recover the FPGA from a faulty behavior in 95% of the cases, which avoids waiting for slower processes such as scrubbing. This real-time detection only requires an extra area of 13% with respect to the unprotected circuit and does not include any loss of precision compared to previous designs. [ABSTRACT FROM AUTHOR]

Communication systems that work in jeopardized environments such as space are affected by soft errors that can cause malfunctions in the behavior of the circuits such as, for example, single event upsets (SEUs) or multiple bit upsets (MBUs). In order to avoid this erroneous functioning, this kind of systems are usually protected using redundant logic such as triple modular redundancy (TMR) or error correction codes (ECCs). After the implementation of the protected modules, the communication modules must be tested to assess the achieved reliability. These tests could be driven into accelerator facilities through ionization processes or they can be performed using fault injection tools based on software simulation such as the SEUs simulation tool (SST), or based on field-programmable gate array (FPGA) emulation like the one described in this work. In this paper, a tutorial for the setup of a fault injection emulation platform based on the Xilinx soft error mitigation (SEM) intellectual property (IP) controller is depicted step by step, showing a complete cycle. To illustrate this procedure, an online repository with a complete project and a step-by-step guide is provided, using as device under test a classical communication component such as a finite impulse response (FIR) filter. Finally, the integration of the automatic configuration memory error-injection (ACME) tool to speed up the fault injection process is explained in detail at the end of the paper. [ABSTRACT FROM AUTHOR]