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Vertical junctionless transistors with a gate-all-around (GAA) structure based on Ge/Si core/shell nanowires epitaxially grown and integrated on a 〈111〉 Si substrate were fabricated and analyzed. Because of efficient gate coupling in the nanowire-GAA transistor structure and the high density one-dimensional hole gas formed in the Ge nanowire core, excellent P-type transistor behaviors with Ion of 750 µA/µm were obtained at a moderate gate length of 544 nm with minimal short-channel effects. The experimental data can be quantitatively modeled by a GAA junctionless transistor model with few fitting parameters, suggesting the nanowire transistors can be fabricated reliably without introducing additional factors that can degrade device performance. Devices with different gate lengths were readily obtained by tuning the thickness of an etching mask film. Analysis of the histogram of different devices yielded a single dominate peak in device parameter distribution, indicating excellent uniformity and high confidence of single nanowire operation. Using two vertical nanowire junctionless transistors, a PMOS-logic inverter with near rail-to-rail output voltage was demonstrated, and device matching in the logic can be conveniently obtained by controlling the number of nanowires employed in different devices rather than modifying device geometry. These studies show that junctionless transistors based on vertical Ge/Si core/shell nanowires can be fabricated in a controlled fashion with excellent performance and may be used in future hybrid, high-performance circuits where bottom-up grown nanowire devices with different functionalities can be directly integrated with an existing Si platform. [ABSTRACT FROM AUTHOR]